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T6963CFG
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6963CFG
DOT MATRIX LCD CONTROLLER LSI
The T6963CFG is an LCD controller designed to be used with LCD control driver LSIs and data display memories. The device has an 8−bit parallel data bus and control lines for reading or writing through an MPU interface. It can be directly connected to a TMPZ−80. It has a 128−word character generator ROM which can control an external display RAM of up to 64 Kbytes. Allocation of text, graphics and external character generator RAM can be made easily and the display window can be moved freely within the allocated memory range. The device supports a very broad range of LCD formats by allowing selection of different combinations via a set of programmable inputs. It can be used in text, graphic and combination text−and−graphic modes, and includes various attribute functions. The T6963CFG is lead (Pb)-free (Sn-Ag) product.
Features
Weight: 1.2 g (typ.)
z Display format (pin−selectable) Columns : 32, 40, 64, 80 Lines : 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32 The combination of number of columns and number of lines must not cause the frequency to exceed 5.5 MHz. (See Fig. 2) z Character font (pin−selectable) Horizontal dots : 5, 6, 7, 8 Vertical dots : 8 (fixed) It is necessary to set a character font in Graphic mode just as in Text mode. The oscillation frequency does not change with the font selection. z Display duty : 1 / 16 to 1 / 128 z A 128−word character generator ROM (code 0101) T6963CFG−0101 is built in as standard. z External display memory : 64 KB Max The addresses in display memory of the text area, graphic area and external character generator area are determined by software. z Read or Write operations from the CPU do not disturb the display. z A crystal oscillator circuit is built in. The oscillation frequency is adjusted according to the display size. If using an external clock, use the XI pin as the clock input. (XO open.) External capacitors Crystal oscillation : 20 to 30 pF Ceramic oscillation : 30 to 100 pF Built−in feedback resistor : 900 kΩ (typ.) z Toshiba LCD driver LSIs (other than these with a built−in RAM) can be connected to the device. z External display RAM must be static RAM. The T6963CFG cannot refresh D−RAM. z The attribute functions can only be used in Text mode. They cannot be used in Graphic or Combination Character mode.
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2007-05-15
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T6963CFG
Block Diagram
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2007-05-15
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T6963CFG
Pin Assignment
Pin Functions
Pin Name I/O Pins for selection of LCD size
DUAL
Functions
H L H H 2 16
H L H L 4 32
H L L H 6 48
H L L L 8 64
H H H H 10 80
H H H L 12 96
H H L H 14
H H L L 16
L L H H 4 32
L L H L 8 64
L L L H 12 96
L L L L 16
L H H H 20
L H H L 24
L H L H 28
L H L L 32
MDS MDS MD0 MD1 Input MD1 MD0 LINES V−DOTS
112 128
128 160 192 224 256 2 SCREENS
1 SCREEN MD2 MD2 MD3 Input Pins for selection of number of columns MD3 Columns FS0 FS0 FS1 Input Pins for selection of font FS1 Font D0 to D7 I/O Input Data I / O pins between CPU and T6963CFG (D7 is MSB) Data Write. Write data into T6963CFG when WR = L. H H 32 H H
L H 40 L H
H L 64 H L
L L 80 L L
5×8 6×8 7×8 8×8
WR
RD
CE
Input Input
Data Read. Read data fromT6963CFG when RD = L. Chip Enable for T6963CFG. CE must be L when CPU communicates with T6963CFG.
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2007-05-15
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T6963CFG
I/O Input Input
Input
Pin Name C/D
Functions
WR = L ······ C / D = H: Command Write
RD = L ······ C / D = H: Status Read
C / D = L: Data Write C / D = L: Data Read
HALT
RESET DSPON
H ······ Normal, L ······ Stops the oscillation of the clock
H ······ Normal (T6963CFG has internal pull−up resistor) L ······ Initialize T6963CFG. Text and graphic have addresses and text and graphic area settings are retained. Control pin for external DC / DC. DSPON is L when HALT is L or RESET is L. (When DSPON goes H, the column drivers are cleared.) H ······ Single−Scan L ······ Dual−Scan H ······ Sending data by odd / even separation L ······ Sending data by simple serial method DUAL SDSEL H H H L L H L L
Output
DUAL
Input
SDSEL
Input
Upper screen Lower screen
HOD, ED ―
ED ―
HOD, ED LOD, ED
ED ED
ce0 (LOD)
ce1 (LSCP)
Output
ce0
at DUAL = H Chip enable pin for display memory in the address range 0000H to 07FFH Serial data output for odd columns in lower area of LCD
LOD at DUAL = L
ce1
Output Output I/O Output Output Output Output Output Output Output Output Input Output Output Input ― ―
at DUAL = H Chip enable pin for display memory in the address range 0800H to 0FFFH Shift clock pulse output for column drivers in lower area of LCD
LSCP at DUAL = L
ce d0 to d7 ad0 to ad15 R/W ED HOD CDATA HSCP LP FR XI XO CH1, CH2
Chip enable pin for display memory of any address Data I / O pins for display memory Address outputs for display memory (ad15 = L: for upper area of LCD, ad15 = H: for lower area of LCD) Read / Write signal for display memory
.