COM90C66 Controller/Transceiver Datasheet

COM90C66 Datasheet, PDF, Equivalent


Part Number

COM90C66

Description

ARCNET Controller/Transceiver

Manufacture

SMSC Corporation

Total Page 30 Pages
Datasheet
Download COM90C66 Datasheet


COM90C66
www.DataSheet4U.com
COM90C66
Data Sheet with Erratas for
Rev. B and Rev. D devices
ARCNET® Controller/Transceiver with
AT® Interface and On-Chip RAM
FEATURES
ARCNET LAN Controller/Transceiver/
Compatible with the SMSC HYC9058/68/ 88
Support Logic/Dual-Port RAM
(COAX and Twisted Pair Drivers)
Integrates SMSC COM90C65 with 16-Bit
Token Passing Protocol with Self
Data Bus, Dual-Port RAM, and Enhanced
Reconfiguration Detection
Diagnostics Circuitry
Variable Data Length Packets
Includes IBM® PC/AT® Bus Interface
16 Bits CRC Check/Generation
Circuitry
Includes Address Decoding Circuitry for On-
Supports 8- and 16-Bit Data Buses
Chip RAM, PROM and I/O
Full 2K x 8 On-Chip Dual-Port Buffer RAM
Supports up to 255 Nodes
Zero Wait State Arbitration for Most AT
Contains Software Accessible Node ID
Buses
Register
SMSC COM90C26 Software Compatible
Compatible with Various Topologies (Star,
Command Chaining Enhances Performance
Tree, Bus, ...)
Supports Memory Mapped and Sequential
On-Board Crystal Oscillator and Reset
I/O Mapped Access to the Internal RAM
Circuitry
Buffer
Low Power CMOS, Single +5V Supply
GENERAL DESCRIPTION
The SMSC COM90C66 is a special purpose device. Maximum integration has been achieved
communications controller for interconnecting by including the 2K x 8 RAM buffer on the chip,
processors and intelligent peripherals using the providing the immediate benefits of a lower
ARCNET Local Area Network. The COM90C66 device pin count and less board components.
is unique in that it integrates the core ARCNET The performance is enhanced in four ways: a
logic found in Standard Microsystems' original 16-bit data bus for operation with the IBM PC/AT;
COM90C26 and COM90C32 with an on-chip 2K a zero wait state arbitration mechanism, due
x 8 RAM, as well as the 16-bit data bus interface partly to the integration of the RAM buffer on-
for the IBM PC/AT. Because of the inclusion of chip; the ability of the device to do consecutive
the RAM buffer in the COM90C66, a complete transmissions and receptions via the Command
ARCNET node can be implemented with only Chaining operation; and improved diagnostics,
one or two additional ICs (8- or 16-bit allowing the user to control the system more
applications, respectively) and a media driver efficiently. For most AT compatibles, the device
circuit. The ARCNET core remains functionally handles zero wait state transfers.
untouched, eliminating validation and
compatibility concerns. The enhancements exist
in the integration and the performance of the
ARCNET is a registered trademark of Datapoint Corporation
IBM, AT, PC/AT and Micro Channel are registered trademarks of
International Business Machines Corporation
1

COM90C66
www.DataSheet4U.com
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................................ 1
GENERAL DESCRIPTION ................................................................................................................................................ 1
PIN CONFIGURATION...................................................................................................................................................... 3
DESCRIPTION OF PIN FUNCTIONS............................................................................................................................... 4
PROTOCOL DESCRIPTION............................................................................................................................................. 9
NETWORK PROTOCOL........................................................................................................................................... 9
NETWORK RECONFIGURATION ........................................................................................................................... 9
BROADCAST MESSAGES ..................................................................................................................................... 10
EXTENDED TIMEOUT FUNCTION ........................................................................................................................ 10
LINE PROTOCOL.................................................................................................................................................... 10
SYSTEM DESCRIPTION..................................................................................................................................................12
MICROPROCESSOR INTERFACE .........................................................................................................................12
TRANSMISSION MEDIA INTERFACE ....................................................................................................................13
FUNCTIONAL DESCRIPTION .........................................................................................................................................13
MICROSEQUENCER ...............................................................................................................................................13
ADDRESS DECODING ............................................................................................................................................19
INTERNAL REGISTERS ..........................................................................................................................................22
INTERNAL RAM .......................................................................................................................................................29
SOFTWARE INTERFACE........................................................................................................................................29
SOFTWARE COMPATIBILITY CONSIDERATIONS ..............................................................................................31
COMMAND CHAINING ............................................................................................................................................32
RESET DETAILS ......................................................................................................................................................34
READ AND WRITE CYCLES ...................................................................................................................................35
NODE ID LOGIC .......................................................................................................................................................43
TRANSMIT/RECEIVE LOGIC ..................................................................................................................................43
IMPROVED DIAGNOSTICS.....................................................................................................................................43
OSCILLATOR ...........................................................................................................................................................45
OPERATIONAL DESCRIPTION ......................................................................................................................................46
MAXIMUM GUARANTEED RATINGS .....................................................................................................................46
DC CHARACTERISTICS..........................................................................................................................................46
TIMING DIAGRAMS .........................................................................................................................................................49
Please see Addendum 1 entitled Data Sheet Errata for Revision B COM90C66, which discusses changes to this
data sheet which apply to the Revision B device, on Page 62.
Please see Addendum 2 entitled Data Sheet Errata for Revision D COM90C66, which discusses changes to this
data sheet which apply to the Revision D device, on Page 64.
80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123
2


Features www.DataSheet4U.com COM90C66 Data Sheet with Erratas for Rev. B and Rev. D dev ices ARCNET® Controller/Transceiver w ith AT® Interface and On-Chip RAM FEAT URES • • • • • • • • ARCNET LAN Controller/Transceiver/ Su pport Logic/Dual-Port RAM Integrates SM SC COM90C65 with 16-Bit Data Bus, Dual- Port RAM, and Enhanced Diagnostics Circ uitry Includes IBM® PC/AT® Bus Interf ace Circuitry Supports 8- and 16-Bit Da ta Buses Full 2K x 8 On-Chip Dual-Port Buffer RAM Zero Wait State Arbitration for Most AT Buses SMSC COM90C26 Softwar e Compatible Command Chaining Enhances Performance Supports Memory Mapped and Sequential I/O Mapped Access to the Int ernal RAM Buffer • • • • • • • • • Compatible with the S MSC HYC9058/68/ 88 (COAX and Twisted Pa ir Drivers) Token Passing Protocol with Self Reconfiguration Detection Variabl e Data Length Packets 16 Bits CRC Check /Generation Includes Address Decoding C ircuitry for OnChip RAM, PROM and I/O Supports up to 255 Nodes Contains Software Accessible Node ID Regis.
Keywords COM90C66, datasheet, pdf, SMSC Corporation, ARCNET, Controller/Transceiver, OM90C66, M90C66, 90C66, COM90C6, COM90C, COM90, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)