ARCNET Controller/Transceiver. COM90C66 Datasheet

COM90C66 Controller/Transceiver. Datasheet pdf. Equivalent


SMSC Corporation COM90C66
www.DataSheet4U.com
COM90C66
Data Sheet with Erratas for
Rev. B and Rev. D devices
ARCNET® Controller/Transceiver with
AT® Interface and On-Chip RAM
FEATURES
ARCNET LAN Controller/Transceiver/
Compatible with the SMSC HYC9058/68/ 88
Support Logic/Dual-Port RAM
(COAX and Twisted Pair Drivers)
Integrates SMSC COM90C65 with 16-Bit
Token Passing Protocol with Self
Data Bus, Dual-Port RAM, and Enhanced
Reconfiguration Detection
Diagnostics Circuitry
Variable Data Length Packets
Includes IBM® PC/AT® Bus Interface
16 Bits CRC Check/Generation
Circuitry
Includes Address Decoding Circuitry for On-
Supports 8- and 16-Bit Data Buses
Chip RAM, PROM and I/O
Full 2K x 8 On-Chip Dual-Port Buffer RAM
Supports up to 255 Nodes
Zero Wait State Arbitration for Most AT
Contains Software Accessible Node ID
Buses
Register
SMSC COM90C26 Software Compatible
Compatible with Various Topologies (Star,
Command Chaining Enhances Performance
Tree, Bus, ...)
Supports Memory Mapped and Sequential
On-Board Crystal Oscillator and Reset
I/O Mapped Access to the Internal RAM
Circuitry
Buffer
Low Power CMOS, Single +5V Supply
GENERAL DESCRIPTION
The SMSC COM90C66 is a special purpose device. Maximum integration has been achieved
communications controller for interconnecting by including the 2K x 8 RAM buffer on the chip,
processors and intelligent peripherals using the providing the immediate benefits of a lower
ARCNET Local Area Network. The COM90C66 device pin count and less board components.
is unique in that it integrates the core ARCNET The performance is enhanced in four ways: a
logic found in Standard Microsystems' original 16-bit data bus for operation with the IBM PC/AT;
COM90C26 and COM90C32 with an on-chip 2K a zero wait state arbitration mechanism, due
x 8 RAM, as well as the 16-bit data bus interface partly to the integration of the RAM buffer on-
for the IBM PC/AT. Because of the inclusion of chip; the ability of the device to do consecutive
the RAM buffer in the COM90C66, a complete transmissions and receptions via the Command
ARCNET node can be implemented with only Chaining operation; and improved diagnostics,
one or two additional ICs (8- or 16-bit allowing the user to control the system more
applications, respectively) and a media driver efficiently. For most AT compatibles, the device
circuit. The ARCNET core remains functionally handles zero wait state transfers.
untouched, eliminating validation and
compatibility concerns. The enhancements exist
in the integration and the performance of the
ARCNET is a registered trademark of Datapoint Corporation
IBM, AT, PC/AT and Micro Channel are registered trademarks of
International Business Machines Corporation
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COM90C66 Datasheet
Recommendation COM90C66 Datasheet
Part COM90C66
Description ARCNET Controller/Transceiver
Feature COM90C66; www.DataSheet4U.com COM90C66 Data Sheet with Erratas for Rev. B and Rev. D devices ARCNET® Control.
Manufacture SMSC Corporation
Datasheet
Download COM90C66 Datasheet




SMSC Corporation COM90C66
www.DataSheet4U.com
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................................ 1
GENERAL DESCRIPTION ................................................................................................................................................ 1
PIN CONFIGURATION...................................................................................................................................................... 3
DESCRIPTION OF PIN FUNCTIONS............................................................................................................................... 4
PROTOCOL DESCRIPTION............................................................................................................................................. 9
NETWORK PROTOCOL........................................................................................................................................... 9
NETWORK RECONFIGURATION ........................................................................................................................... 9
BROADCAST MESSAGES ..................................................................................................................................... 10
EXTENDED TIMEOUT FUNCTION ........................................................................................................................ 10
LINE PROTOCOL.................................................................................................................................................... 10
SYSTEM DESCRIPTION..................................................................................................................................................12
MICROPROCESSOR INTERFACE .........................................................................................................................12
TRANSMISSION MEDIA INTERFACE ....................................................................................................................13
FUNCTIONAL DESCRIPTION .........................................................................................................................................13
MICROSEQUENCER ...............................................................................................................................................13
ADDRESS DECODING ............................................................................................................................................19
INTERNAL REGISTERS ..........................................................................................................................................22
INTERNAL RAM .......................................................................................................................................................29
SOFTWARE INTERFACE........................................................................................................................................29
SOFTWARE COMPATIBILITY CONSIDERATIONS ..............................................................................................31
COMMAND CHAINING ............................................................................................................................................32
RESET DETAILS ......................................................................................................................................................34
READ AND WRITE CYCLES ...................................................................................................................................35
NODE ID LOGIC .......................................................................................................................................................43
TRANSMIT/RECEIVE LOGIC ..................................................................................................................................43
IMPROVED DIAGNOSTICS.....................................................................................................................................43
OSCILLATOR ...........................................................................................................................................................45
OPERATIONAL DESCRIPTION ......................................................................................................................................46
MAXIMUM GUARANTEED RATINGS .....................................................................................................................46
DC CHARACTERISTICS..........................................................................................................................................46
TIMING DIAGRAMS .........................................................................................................................................................49
Please see Addendum 1 entitled Data Sheet Errata for Revision B COM90C66, which discusses changes to this
data sheet which apply to the Revision B device, on Page 62.
Please see Addendum 2 entitled Data Sheet Errata for Revision D COM90C66, which discusses changes to this
data sheet which apply to the Revision D device, on Page 64.
80 Arkay Drive
Hauppauge, NY 11788
(516) 435-6000
FAX (516) 273-3123
2



SMSC Corporation COM90C66
www.DataSheet4U.com
For other machines, the IOCHRDY signal may
be briefly negated to give the device the extra
time necessary to support the faster machines.
Aside from the implementation of a 16-bit data
bus interface, the remaining bus interface logic
is identical to that found in the SMSC
COM90C65, which contains all the support logic
circuitry.
The ARCNET Local Area Network is a token
passing network which operates at a 2.5 Mbps
data rate. A token passing protocol provides
predictable response times because each
network event occurs within a known time
interval. Throughput can be reliably predeter-
mined based upon the number of nodes and
their expected traffic.
The COM90C66 establishes the network
configuration and automatically reconfigures the
token passing order as new nodes are added or
deleted from the network.
The COM90C66 performs address recognition,
CRC checking and generation, packet
acknowledgement, and other network
management functions. The C0M90C66
interfaces directly to the IBM PC/AT or
compatibles. The internal 2K x 8 RAM buffer is
used to hold up to four data packets with a
maximum length of 508 bytes each.
PIN CONFIGURATION
AEN
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
INTR
nBSLED
nTXLED
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12 74
13 73
14 72
15 71
16 70
17 69
18 68
19 67
20 66
21
22
COM90C66
65
64
23 63
24 62
25 61
26 60
27 59
28 58
29 57
30 56
31 55
32 54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
BALE
nSBHE
nOWS
IOCHRDY
nMEMCS16
nIOCS16
GND
nMEMW
nMEMR
nIOW
nIOR
nTOPL
nTOPH
NC
NC
CACLK
CLK
RXIN
nPULSE2
nPULSE1
nPROM
PACKAGE: 84-Pin P3LCC
Ordering Information: COM90C66 LJP







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