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BSI
Very Low Power/Voltage CMOS SRAM 512K X 8 bit
DESCRIPTION
BS62LV4007
FEATURES
• Vcc operation voltage : 4.5V ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade: 68mA (@55ns) operating current I -grade: 70mA (@55ns) operating current C-grade: 58mA (@70ns) operating current I -grade: 60mA (@70ns) operating current 2.0uA (Typ.) CMOS standby current • High speed access time : -55 55ns -70 70ns • Automatic power down when chip is deselected • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • Three state outputs and TTL compatible
The BS62LV4007 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 2.0uA at 5.0V/25oC and maximum access time of 55ns at 5.0V/85oC. Easy memory expansion is provided by an active LOW chip enable (CE) , and active LOW output enable (OE) and three-state output drivers. The BS62LV4007 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP , PDIP, TSOP II and STSOP package.
PRODUCT FAMILY
PRODUCT FAMILY
BS62LV4007TC BS62LV4007STC BS62LV4007SC BS62LV4007EC BS62LV4007PC BS62LV4007TI BS62LV4007STI BS62LV4007SI BS62LV4007EI BS62LV4007PI
OPERATING TEMPERATURE
Vcc RANGE
SPEED ( ns )
55ns :4.5~5.5V 70ns :4.5~5.5V
POWER DISSIPATION
( I CCSB1 , Max )
STANDBY
Vcc =5.0V
Operating
( I CC , Max )
Vcc = 5.0V
55ns
Vcc =5.0V
70ns
PKG TYPE TSOP - 32 STSOP -32 SOP - 32 TSOP2 - 32 PDIP - 32 TSOP - 32 STSOP - 32 SOP - 32 TSOP2 - 32 PDIP - 32
+0 C to +70 C
O
O
4.5V ~ 5.5V
55 / 70
30uA
68mA
58mA
- 40
O
C to +85 C
O
4.5V ~ 5.5V
55 / 70
60uA
70mA
60mA
PIN CONFIGURATIONS
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
BLOCK DIAGRAM
A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4
•
BS62LV4007SC BS62LV4007SI BS62LV4007EC BS62LV4007EI BS62LV4007PC BS62LV4007PI
Address Input Buffer
22
Row Decoder
2048
Memory Array 2048 X 2048
2048 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 8 Data Input Buffer 8 Column I/O Write Driver Sense Amp 256 Column Decoder 16 CE WE OE Vdd GND A11 A9 A8 A3 A2 A1 A0 A10 Control Address Input Buffer
8
A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
BS62LV4007TC BS62LV4007STC BS62LV4007TI BS62LV4007STI
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
Data Output Buffer
8
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS62LV4007
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1
Revision 1.