ANALOG-TO-DIGITAL CONVERTER. ADS1218 Datasheet

ADS1218 CONVERTER. Datasheet pdf. Equivalent


Burr-Brown ADS1218
BurrĆBrown Products
from Texas Instruments
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER with FLASH Memory
FEATURES
24 BITS NO MISSING CODES
0.0015% INL
22 BITS EFFECTIVE RESOLUTION (PGA = 1),
19 BITS (PGA = 128)
4K BYTES OF FLASH MEMORY
PROGRAMMABLE FROM 2.7V TO 5.25V
PGA FROM 1 TO 128
SINGLE CYCLE SETTLING MODE
PROGRAMMABLE DATA OUTPUT RATES UP
TO 1kHz
PRECISION ON-CHIP 1.25V/2.5V REFERENCE:
ACCURACY: 0.2%
DRIFT: 5ppm/°C
EXTERNAL DIFFERENTIAL REFERENCE OF
0.1V TO 2.5V
ON-CHIP CALIBRATION
PIN-COMPATIBLE WITH ADS1216
SPI™ COMPATIBLE
2.7V TO 5.25V
< 1mW POWER CONSUMPTION
APPLICATIONS
INDUSTRIAL PROCESS CONTROL
LIQUID/GAS CHROMATOGRAPHY
BLOOD ANALYSIS
SMART TRANSMITTERS
PORTABLE INSTRUMENTATION
WEIGHT SCALES
PRESSURE TRANSDUCERS
DESCRIPTION
The ADS1218 is a precision, wide dynamic range,
delta-sigma, Analog-to-Digital (A/D) converter with
24-bit resolution and Flash memory operating from
2.7V to 5.25V supplies. The delta-sigma, A/D
converter provides up to 24 bits of no missing code
performance and effective resolution of 22 bits.
The eight input channels are multiplexed. Internal
buffering can be selected to provide a very high input
impedance for direct connection to transducers or
low-level voltage signals. Burnout current sources are
provided that allow for the detection of an open or
shorted sensor. An 8-bit Digital-to-Analog (D/A)
converter provides an offset correction with a range
of 50% of the FSR (Full-Scale Range).
The PGA (Programmable Gain Amplifier) provides
selectable gains of 1 to 128 with an effective
resolution of 19 bits at a gain of 128. The A/D
conversion is accomplished with a second-order
delta-sigma modulator and programmable sinc filter.
The reference input is differential and can be used for
ratiometric conversion. The on-board current DACs
(Digital-to-Analog Converters) operate independently
with the maximum current set by an external resistor.
The serial interface is SPI-compatible. Eight bits of
digital I/O are also provided that can be used for input
or output. The ADS1218 is designed for
high-resolution measurement applications in smart
transmitters, industrial process control, weight scales,
chromatography, and portable instrumentation.
AGND AVDD
RDAC
VREFOUT
VRCAP
VREF+
VREF
XIN
XOUT
IDAC2
IDAC1
8−Bit
IDAC
8−Bit
IDAC
1.25V or
2.5V
Reference
Clock Generator
Offset
DAC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
MUX
BUF
+ PGA
Digital I/O
Interface
DVDD DGND BUFEN
D0 ... D7
2nd−Order
Modulator
Program−
mable
Digital
F ilter
Registers
Controller
RAM
4K Bytes
FLASH
WREN
Serial Interface
PDWN DSYNC RESET DRDY
POL
SCLK
DIN
DOUT
CS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI is a trademark of Motorola.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2005, Texas Instruments Incorporated


ADS1218 Datasheet
Recommendation ADS1218 Datasheet
Part ADS1218
Description 24-Bit ANALOG-TO-DIGITAL CONVERTER
Feature ADS1218; BurrĆBrown Products from Texas Instruments ADS1218 SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2.
Manufacture Burr-Brown
Datasheet
Download ADS1218 Datasheet




Burr-Brown ADS1218
ADS1218
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
AVDD to AGND
DVDD to DGND
Input Current
Input Current
AIN
AVDD to DVDD
AGND to DGND
Digital Input Voltage to GND
Digital Output Voltage to GND
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10s)
–0.3V to +6V
–0.3V to +6V
100mA, Momentary
10mA, Continuous
GND – 0.5V to AVDD + 0.5V
–6V to +6V
–0.3V to +0.3V
–0.3V to DVDD + 0.3V
–0.3V to DVDD + 0.3V
+150°C
–40°C to +85°C
–60°C to +100°C
+300°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
2



Burr-Brown ADS1218
ADS1218
www.ti.com
SBAS187C – SEPTEMBER 2001 – REVISED SEPTEMBER 2005
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On,
RDAC = 150k, VREF (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT (AIN0 – AIN7, AINCOM)
Analog Input Range
Full-Scale Input Voltage Range
Differential Input Impedance
Buffer Off
Buffer On
(In+) – (In–), See Block Diagram
Buffer Off
AGND – 0.1
AGND + 0.05
5/PGA
AVDD + 0.1
AVDD – 1.5
±VREF/PGA
V
V
V
M
Input Current
Buffer On
0.5 nA
Bandwidth
Fast Settling Filter
Sinc2 Filter
–3dB
–3dB
0.469 × fDATA
0.318 × fDATA
Hz
Hz
Sinc3 Filter
–3dB
0.262 × fDATA
Hz
Programmable Gain Amplifier
User-Selectable Gain Ranges
1
128
Input Capacitance
9 pF
Input Leakage Current
Modulator Off, T = +25°C
5 pA
Burnout Current Sources
2 µA
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
±VREF/(2 × PGA)
8
V
Bits
Offset DAC Gain Error
±10 %
Offset DAC Gain Error Drift
1 ppm/°C
SYSTEM PERFORMANCE
Resolution
24 Bits
No Missing Codes
sinc3
24 Bits
Integral Nonlinearity
End Point Fit
±0.0015
% of FS
Offset Error(1)
Before Calibration
7.5 ppm of FS
Offset Drift(1)
0.02
ppm of FS/°C
Gain Error
After Calibration
0.005
%
Gain Error Drift(1)
0.5 ppm/°C
Common-Mode Rejection
at DC
100
dB
Normal-Mode Rejection
Output Noise
fCM = 60Hz, fDATA = 10Hz
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
fSIG = 50Hz, fDATA = 50Hz
fSIG = 60Hz, fDATA = 60Hz
130
120
120
100
100
See Typical Characteristics
dB
dB
dB
dB
dB
Power-Supply Rejection
VOLTAGE REFERENCE INPUT
at DC, dB = –20 log(VOUT/VDD)(2)
80
95
dB
Reference Input Range
VREF
Common-Mode Rejection
REF IN+, REF IN–
VREF (REF IN+) – (REF IN–)
at DC
0
0.1
AVDD
V
2.5 2.6 V
120 dB
Common-Mode Rejection
Bias Current(3)
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 2.5V
120 dB
1.3 µA
(1) Calibration can minimize these errors.
(2) VOUT is change in digital result.
(3) 12pF switched capacitor at fSAMP clock frequency.
3







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