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N80C58 Dataheets PDF



Part Number N80C58
Manufacturers Intel
Logo Intel
Description (N80Cxx) CHMOS Single-Chip 8-Bit Microcontroller
Datasheet N80C58 DatasheetN80C58 Datasheet (PDF)

www.DataSheet4U.com 8XC52 54 58 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C52 80C52 80C32 87C54 80C54 87C58 80C58 See Table 1 for Proliferation Options Y High Performance CHMOS EPROM ROM CPU 12 24 33 MHz Operations Three 16-Bit Timer Counters Programmable Clock Out Up Down Timer Counter Three Level Program Lock System 8K 16K 32K On-Chip Program Memory 256 Bytes of On-Chip Data RAM Improved Quick Pulse Programming Algorithm Boolean Processor 32 Programmable I O Lines Y Y 6.

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www.DataSheet4U.com 8XC52 54 58 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial Express 87C52 80C52 80C32 87C54 80C54 87C58 80C58 See Table 1 for Proliferation Options Y High Performance CHMOS EPROM ROM CPU 12 24 33 MHz Operations Three 16-Bit Timer Counters Programmable Clock Out Up Down Timer Counter Three Level Program Lock System 8K 16K 32K On-Chip Program Memory 256 Bytes of On-Chip Data RAM Improved Quick Pulse Programming Algorithm Boolean Processor 32 Programmable I O Lines Y Y 6 Interrupt Sources Programmable Serial Channel with Framing Error Detection Automatic Address Recognition TTL and CMOS Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space MCS 51 Microcontroller Compatible Instruction Set Power Saving Idle and Power Down Modes ONCE (On-Circuit Emulation) Mode Four-Level Interrupt Priority Extended Temperature Range Except for 33 MHz Offering ( b 40 C to a 85 C) Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y MEMORY ORGANIZATION ROM Device 80C52 80C54 80C58 EPROM Version 87C52 87C54 87C58 ROMless Version 80C32 80C32 80C32 ROM EPROM Bytes 8K 16K 32K RAM Bytes 256 256 256 These devices can address up to 64 Kbytes of external program data memory The Intel 8XC52 8XC54 8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC52 8XC54 8XC58 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with the existing MCS 51 family of products The 8XC52 8XC54 8XC58 is an enhanced version of the 87C51 80C51BH 80C31BH The added features make it an even more powerful microcontroller for applications that require clock output and up down counting capabilities such as motor control It also has a more versatile serial channel that facilitates multi-processor communications Throughout this document 8XC5X will refer to the 8XC52 80C32 8XC54 and 8XC58 unless information applies to a specific device Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 2004 July, 2004 Order Number: 272336-005 8XC52 54 58 www.DataSheet4U.com Table 1 Proliferations Options Standard 1 80C32 80C52 87C52 80C54 87C54 80C58 87C58 X X X X X X X -1 X X X X X X X -2 X X X X X X X -24 X X X X X X X -33 X X X X X X X NOTES 1 35 -1 3 5 -2 0 5 -24 3 5 -33 3 5 MHz MHz MHz MHz MHz to to to to to 12 16 12 24 33 MHz MHz MHz MHz MHz 5V 5V 5V 5V 5V g 20% g 20% g 20% g 20% g 10% 272336 – 1 Figure 1 8XC5X Block Diagram 2 www.DataSheet4U.com 8XC52/54/58 PROCESS INFORMATION This device is manufactured on P629.0, a CHMOS III-E process. Additional process and reliability information is available in the Intel® Quality System Handbook . PACKAGES 40-Pin Plastic DIP (OTP) 40-Pin CERDIP (EPROM) 44-Pin PLCC (OTP) 44-Pin QFP (OTP) PLCC DIP 272336 – 2 272336 – 3 * Do not connect reserved pins. QFP Figure 2. Pin Connections 272336 – 4 3 8XC52 54 58 www.DataSheet4U.com pins that are externally pulled low will source current (IIL on the data sheet) because of the internal pullups Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX DPTR) In this application it uses strong internal pullups when emitting 1’s During accesses to external Data Memory that use 8-bit addresses (MOVX Ri) Port 2 emits the contents of the P2 Special Function Register Some Port 2 pins receive the high-order address bits during EPROM programming and program verification Port 3 Port 3 is an 8-bit bidirectional I O port with internal pullups The Port 3 output buffers can drive LS TTL inputs Port 3 pins that have 1’s written to them are pulled high by the internal pullups and in that state can be used as inputs As inputs Port 3 pins that are externally pulled low will source current (IIL on the data sheet) because of the pullups Port 3 also serves the functions of various special features of the 8051 Family as listed below Port Pin P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 P3 6 P3 7 Alternate Function RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (Timer 0 external input) T1 (Timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) PIN DESCRIPTIONS VCC Supply voltage VSS Circuit ground VSS1 Secondary ground (not on DIP) Provided to reduce ground bounce and improve power supply by-passing NOTE This pi.


N80C54 N80C58 FMRX1-xxxF


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