26LV800BTC MX26LV800BTC Datasheet

26LV800BTC Datasheet, PDF, Equivalent


Part Number

26LV800BTC

Description

MX26LV800BTC

Manufacture

Macronix International

Total Page 30 Pages
Datasheet
Download 26LV800BTC Datasheet


26LV800BTC
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FEATURES
MX26LV800T/B
Macronix NBitTM Memory Family
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE
3V ONLY HIGH SPEED eLiteFlashTM MEMORY
• Extended single - supply voltage range 3.0V to 3.6V
• 1,048,576 x 8/524,288 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55/70ns
• Low power consumption
- 30mA maximum active current
- 30uA typical standby current
• Command register architecture
- Byte/word Programming (55us/70us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase verify capability.
- Automatically program and verify data at specified
address
• Status Reply
- Data# polling & Toggle bit for detection of program
and erase operation completion.
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion.
• 2,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Package type:
- 48-pin TSOP
- 48-ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX26LV800T/B is a 8-mega bit high speed Flash
memory organized as 1M bytes of 8 bits or 512K words
of 16 bits. MXIC's high speed Flash memories offer the
most cost-effective and reliable read/write non-volatile
random access memory. The MX26LV800T/B is pack-
aged in 48-pin TSOP, and 48-ball CSP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX26LV800T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX26LV800T/B has separate chip enable (CE#) and
output enable (OE#) controls.
MXIC's high speed Flash memories augment EPROM
functionality with in-circuit electrical erasure and program-
ming. The MX26LV800T/B uses a command register to
manage this functionality. The command register allows
for 100% TTL level control inputs and fixed power sup-
ply levels during erase and programming, while main-
taining maximum EPROM compatibility.
MXIC high speed Flash technology reliably stores
memory contents even after 2,000 erase and program
cycles. The MXIC cell is designed to optimize the erase
and programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low in-
ternal electric fields for erase and program operations
produces reliable cycling. The MX26LV800T/B uses a
3.0V~3.6V VCC supply to perform the High Reliability
Erase and auto Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
P/N:PM1007
REV. 1.3, APR. 13, 2005
1

26LV800BTC
www.DataSheet4U.com
MX26LV800T/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MX26LV800T/B
48 A16
47 BYTE#
46 GND
45 Q15/A-1
44 Q7
43 Q14
42 Q6
41 Q13
40 Q5
39 Q12
38 Q4
37 VCC
36 Q11
35 Q3
34 Q10
33 Q2
32 Q9
31 Q1
30 Q8
29 Q0
28 OE#
27 GND
26 CE#
25 A0
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18 Address Input
Q0~Q14 Data Input/Output
Q15/A-1 Q15(Word mode)/LSB addr(Byte mode)
CE# Chip Enable Input
WE#
Write Enable Input
BYTE# Word/Byte Selection input
RESET# Hardware Reset Pin
OE# Output Enable Input
RY/BY# Ready/Busy Output
VCC
Power Supply Pin (3.0V~3.6V)
GND
Ground Pin
48-Ball CSP Ball Pitch = 0.8 mm, Top View, Balls Facing Down
ABCDE FGH
6 A13 A12 A14 A15 A16 BYTE# Q15/A-1 GND
5 A9
A8 A10 A11 Q7 Q14 Q13 Q6
4 WE# RESET# NC NC Q5 Q12 Vcc Q4
3 RY/BY# NC A18 NC Q2 Q10 Q11 Q3
2 A7 A17 A6 A5 Q0 Q8 Q9 Q1
1 A3 A4 A2 A1 A0 CE# OE# GND
P/N:PM1007
REV. 1.3, APR. 13, 2005
2


Features www.DataSheet4U.com MX26LV800T/B Macron ix NBit TM Memory Family 8M-BIT [1Mx8/5 12K x16] CMOS SINGLE VOLTAGE 3V ONLY HI GH SPEED eLiteFlashTM MEMORY FEATURES Extended single - supply voltage ran ge 3.0V to 3.6V • 1,048,576 x 8/524,2 88 x 16 switchable • Single power sup ply operation - 3.0V only operation for read, erase and program operation • Fast access time: 55/70ns • Low power consumption - 30mA maximum active curr ent - 30uA typical standby current • Command register architecture - Byte/wo rd Programming (55us/70us typical) - Se ctor Erase (Sector structure 16K-Bytex1 , 8K-Bytex2, 32K-Bytex1, and 64K-Byte x 15) • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase verif y capability. - Automatically program a nd verify data at specified address • Status Reply - Data# polling & Toggle bit for detection of program and erase operation completion. • Ready/Busy# p in (RY/BY#) - Provides a hardware method of detecting program or erase operation .
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