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Delay Buffer. CY2SSTU877 Datasheet

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Delay Buffer. CY2SSTU877 Datasheet






CY2SSTU877 Buffer. Datasheet pdf. Equivalent




CY2SSTU877 Buffer. Datasheet pdf. Equivalent





Part

CY2SSTU877

Description

10-Output JEDEC-Compliant Zero Delay Buffer



Feature


www.DataSheet4U.com PRELIMINARY CY2SST U877 1.8V, 500-MHz, 10-Output JEDEC-Co mpliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten diffe rential outputs from one differential i nput • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 40 ps Very low skew: < 40 ps • Power man agement control input • 1.8V ope.
Manufacture

Cypress Semiconductor

Datasheet
Download CY2SSTU877 Datasheet


Cypress Semiconductor CY2SSTU877

CY2SSTU877; ration • Fully JEDEC-compliant • 52- ball BGA and a 40-pin MLF (QFN) This ph ase-locked loop (PLL) clock buffer is d esigned for a VDD of 1.8V, an AVDD of 1 .8V and differential data input and out put levels. Package options include a p lastic 52-ball VFBGA and a 40-pin MLF ( QFN). The device is a zero delay buffer that distributes a differential clock input pair (CK, CK#) t.


Cypress Semiconductor CY2SSTU877

o ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair feedback clock outputs (FBOUT, FB OUT#). The input clocks (CK, CK#), the feedback clocks (FBIN, FBIN#), the LVCM OS (OE, OS), and the analog power input (AVDD) control the clock outputs. The PLL in the CY2SSTU877 clock driver uses the input clocks (CK, CK#) and the fee dback clocks (FBIN.


Cypress Semiconductor CY2SSTU877

, FBIN#) to provide high-performance, lo w-skew, low-jitter output differential clocks (Y[0:9], Y#[0:9]). The CY2SSTU87 7 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. When A VDD is grounded, the PLL is turned off and bypassed for test purposes. When bo th clock signals (CK, CK#) are logic lo w, the device will enter a low-power mo de. An input logic.

Part

CY2SSTU877

Description

10-Output JEDEC-Compliant Zero Delay Buffer



Feature


www.DataSheet4U.com PRELIMINARY CY2SST U877 1.8V, 500-MHz, 10-Output JEDEC-Co mpliant Zero Delay Buffer Features • Operating frequency: 125 MHz to 500 MHz • Supports DDRII SDRAM • Ten diffe rential outputs from one differential i nput • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 40 ps Very low skew: < 40 ps • Power man agement control input • 1.8V ope.
Manufacture

Cypress Semiconductor

Datasheet
Download CY2SSTU877 Datasheet




 CY2SSTU877
www.DataSheet4U.com
PRELIMINARY
CY2SSTU877
1.8V, 500-MHz, 10-Output JEDEC-Compliant
Zero Delay Buffer
Features
• Operating frequency: 125 MHz to 500 MHz
• Supports DDRII SDRAM
• Ten differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 40 ps
• Very low skew: < 40 ps
• Power management control input
• 1.8V operation
• Fully JEDEC-compliant
• 52-ball BGA and a 40-pin MLF (QFN)
Functional Description
The CY2SSTU877 is a high-performance, low-skew, low-jitter
zero delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTU877 generates ten
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTU877 features differential
feedback clock outputs and inputs. This allows the
CY2SSTU877 to be used as a zero delay buffer. When used
as a zero delay buffer in nested clock trees, the CY2SSTU877
locks onto the input reference and translates with near zero
delay to low-skew outputs.
This phase-locked loop (PLL) clock buffer is designed for a
VDD of 1.8V, an AVDD of 1.8V and differential data input and
output levels. Package options include a plastic 52-ball
VFBGA and a 40-pin MLF (QFN). The device is a zero delay
buffer that distributes a differential clock input pair (CK, CK#)
to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one
differential pair feedback clock outputs (FBOUT, FBOUT#).
The input clocks (CK, CK#), the feedback clocks (FBIN,
FBIN#), the LVCMOS (OE, OS), and the analog power input
(AVDD) control the clock outputs.
The PLL in the CY2SSTU877 clock driver uses the input
clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to
provide high-performance, low-skew, low-jitter output differ-
ential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able
to track Spread Spectrum Clocking (SSC) for reduced EMI.
When AVDD is grounded, the PLL is turned off and bypassed
for test purposes. When both clock signals (CK, CK#) are logic
low, the device will enter a low-power mode. An input logic
detection circuit on the differential inputs, independent from
the input buffers, will detect the logic low level and perform a
low-power state where all outputs, the feedback, and the PLL
are OFF. When the inputs transition from both being logic low
to being differential signals, the PLL will be turned back on, the
inputs and outputs will be enabled and the PLL will obtain
phase lock between the feedback clock pair (FBIN, FBIN#)
and the input clock pair (CK, CK#) within the specified stabili-
zation time tL.
Block Diagram
Pin Configuration
52 BGA
12 3 4
A Y1
Y0
Y0# Y5#
B Y1#
GND
GND
GND
C Y2#
GND
NB
NB
D Y2 VDDQ VDDQ VDDQ
E CK VDDQ
NB
NB
F CK# VDDQ
NB
NB
G AGND VDDQ VDDQ VDDQ
H AVDD GND
NB
NB
J Y3
GND
GND
GND
K Y3#
Y4#
Y4
Y9
5
Y5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
Y5#
6
Y6
Y6#
Y7#
Y7
FBIN
FBIN#
FBOUT#
FBOUT
Y8
Y8#
VDDQ
Y2#
Y2
CLK
CLK#
VDDQ
AGND
AVDD
VDDQ
GND
40 39 38
1
37 36
35
34
33 32
31 30
2 29
3 28
4 40 QFN
5 CY2SSTU877
27
26
6 25
7 24
8 23
9 22
10 11 12 13 14 15 16 17 18 19 20 21
Y7#
Y7
VDDQ
FBIN
FBIN#
FBOUT#
FBOUT
VDDQ
OE
OS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07575 Rev. *B
Revised January 19, 2005




 CY2SSTU877
www.DataSheet4U.com
PRELIMINARY
CY2SSTU877
Pin Description
Pin No.
(BGA)
QFN
Name
G1 7
AGND
H1 8
AVDD
E1, F1
4, 5
CLK, CLK#
E6, F6
27, 26
FBIN, FBIN#
H6, G6
24, 25
FBOUT, FBOUT#
B2, B3, B4, B5, C2, 10
C5, H2, H5, J2, J3,
J4, J5
GND
F5 22
OE
D5 21
OS
D2, D3, D4, E2, E5, 1, 6, 9, 15, 20, 23, 28, VDDQ
F2, G2, G3, G4, G5 31, 36
A2, A1, D1, J1, K3, 38, 39, 3, 11, 14, 34, Y [0:9]
A5, A6, D6, J6, K4, 33, 29, 19, 16
A3, B1, C1, K1, K2, 37, 40, 2, 12, 13, 35, Y# [0:9]
A4, B6, C6, K6, K5 32, 30, 18, 17
Description
Ground for 1.8V analog supply
1.8V analog supply
Differential clock input with a (10K–100K) pull-down resistor
Feedback differential clock input
Feedback differential clock output
Ground
Output enable (ASYNC) for Y[0:9] and Y# [0:9]
Output Select (Tied to GND or VCC)
1.8V supply
Buffered output of input clock, CLK
Buffered output of input clock, CLK
Table 1. Function Table
AVDD
GND
GND
GND
GND
VDD
VDD
VDD
VDD
VDD
X
Inputs
OE OS
HX
HX
LH
LL
LH
LL
HX
HX
XX
XX
CLK
L
H
L
H
L
H
L
H
L
H
CLK#
H
L
H
L
H
L
H
L
L
H
Y
L
H
Lz
Lz,Y7 Active
Lz
Lz,Y7 Active
L
H
Lz
Outputs
Y# FBOUT
HL
LH
Lz L
Lz,Y7# Active
H
Lz L
Lz,Y7# Active
H
HL
LH
Lz Lz
Reserved
FBOUT#
H
L
H
L
H
L
H
L
Lz
PLL
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
On
On
On
On
Off
Recommended Operating Conditions
Parameter
Description
TA (Ind.)
TA (Com.)
VDD
Ambient Operating Temp
Ambient Operating Temp
Operating Voltage
Condition
Min.
–40
0
1.7
Max.
85
70
1.9
Unit
°C
°C
V
Document #: 38-07575 Rev. *B
Page 2 of 9




 CY2SSTU877
www.DataSheet4U.com
PRELIMINARY
CY2SSTU877
Absolute Maximum Conditions
Parameter
VIN
VOUT
TS
VCC
IIK
IOK
IO
Description
Input Voltage Range
Output Voltage Range
Storage Temperature
Supply Voltage Range
Input Clamp Current
Output Clamp Current
Continuous Output Current
Continuous Current through VDD/GND
Condition
Min.
–0.5
–0.5
–65
–0.5
–50
–50
–50
–100
Max.
VDDQ + 0.5
VDDQ + 0.5
150
2.5
50
50
50
100
Unit
V
V
°C
V
mA
mA
mA
mA
DC Electrical Specifications
Parameter
VIX
VID DC
VID AC
VIL
VIH
VOL
VOH
IOH
IOL
VIK
VOD
VOX
Description
Conditions
Input Differential Crossing Voltage
Input Differential Voltage (DC Values)
Input Differential Voltage (AC Values)
Input Low Voltage
(OE, OS, CK, CK#)
Input High Voltage
(OE, OS, CK, CK#)
Output Low Voltage
Output High Voltage
Output High Current
IOL = 100 µA
IOL = 9 mA
IOH = –100 µA
IOH = –9 mA
Output Low Current
Input Clamping Voltage
Output Differential Voltage
II = –18 mA
Output Differential Crossing Voltage
Min.
(VDDQ/2) – 0.15
0.3
0.6
0.65 * VDDQ
VDDQ – 0.2
1.1
0.5
VDDQ/2 – 0.08
Max.
(VDDQ/2) + 0.15
VDDQ + 0.4
VDDQ + 0.4
0.35 * VDDQ
0.1
0.6
–9
9
–1.2
VDDQ/2 + 0.08
Unit
V
V
V
V
V
V
V
V
V
mA
mA
V
V
V
AC Electrical Specifications
Parameter
SLR(O)
SLR(I)
CIN
COUT
CIN(DELTA)
Description
Output Slew Rate
Input Slew Rate
Input Capacitance
Conditions
Y[0:9], Y#[0:9], FBOUT,
FBOUT#
CLK, CLK#, FBIN, FBIN#
OE
(Input Capacitance of CK, CK#,
FBIN, FBIN#) Vi = VDDQ or
GND
Ci(delta) (CK, CK#, FBIN,
FBIN#) Vi = VDDQ or GND
Min.
1.5
1
0.5
2
–0.25
Max.
3
4
3
0.25
Unit
V/ns
V/ns
V/ns
pF
pF
pF
AC Timing Specifications
Parameter
FCLK
TDC
TLOCK
Tjitt (cc)
Tjit (Period)
Description
Clock Frequency
Duty Cycle
PLL Lock Time
Cycle-to-cycle jitter
Period Cycle-to-cycle jitter
Conditions
Min.
125
40
–30
–40
Max.
500
60
10
30
20
Unit
MHz
%
µs
ps
ps
Document #: 38-07575 Rev. *B
Page 3 of 9



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