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Buffer PC2700-/PC3200-Compliant. CY2SSTV16859 Datasheet

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Buffer PC2700-/PC3200-Compliant. CY2SSTV16859 Datasheet






CY2SSTV16859 PC2700-/PC3200-Compliant. Datasheet pdf. Equivalent




CY2SSTV16859 PC2700-/PC3200-Compliant. Datasheet pdf. Equivalent





Part

CY2SSTV16859

Description

13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant



Feature


www.DataSheet4U.com CY2SSTV16859 13-Bi t to 26-Bit Registered Buffer PC2700-/P C3200-Compliant Features • Differenti al clock inputs up to 280 MHz • Suppo rts LVTTL switching levels on the RESET # pin • Output drivers have controlle d edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 m A per JESD78, Class II • 64-.
Manufacture

Cypress Semiconductor

Datasheet
Download CY2SSTV16859 Datasheet


Cypress Semiconductor CY2SSTV16859

CY2SSTV16859; pin TSSOP/JEDEC and 56-pin QFN package a vailability • JEDEC specification sup ported The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of f requency up to 280 MHz. Data are regist ered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disab led, and undriven (floating) data and c lock inputs are allo.


Cypress Semiconductor CY2SSTV16859

wed. The LVCMOS RESET# input must always be held at a valid logic high or low l evel. To ensure defined outputs from th e register before a stable clock has be en supplied, RESET# must be held in the low state during power up. In the DDR DIMM application, RESET# is completely asynchronous with respect to CLK# and C LK. Therefore, no timing relationship c an be guaranteed b.


Cypress Semiconductor CY2SSTV16859

etween the two. When entering reset, the register is cleared and the outputs ar e driven low quickly, relative to the t ime to disable the differential input r eceivers, thus ensuring no glitches on the output. However, when coming out of reset, the register becomes active qui ckly, relative to the time to enable th e differential input receivers. Descri ption This 13-bit .

Part

CY2SSTV16859

Description

13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant



Feature


www.DataSheet4U.com CY2SSTV16859 13-Bi t to 26-Bit Registered Buffer PC2700-/P C3200-Compliant Features • Differenti al clock inputs up to 280 MHz • Suppo rts LVTTL switching levels on the RESET # pin • Output drivers have controlle d edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 m A per JESD78, Class II • 64-.
Manufacture

Cypress Semiconductor

Datasheet
Download CY2SSTV16859 Datasheet




 CY2SSTV16859
www.DataSheet4U.com
CY2SSTV16859
13-Bit to 26-Bit Registered Buffer
PC2700-/PC3200-Compliant
Features
• Differential clock inputs up to 280 MHz
• Supports LVTTL switching levels on the RESET# pin
• Output drivers have controlled edge rates, so no
external resistors are required.
• Two KV ESD protection
• Latch-up performance exceeds 100 mA per JESD78,
Class II
• 64-pin TSSOP/JEDEC and 56-pin QFN package avail-
ability
• JEDEC specification supported
Description
This 13-bit to 26-bit registered buffer is designed for 2.3V to
2.7 VDD operations.
All inputs are compatible with the JEDEC Standard for SSTL-2,
except the LVCMOS reset (RESET#) input. All outputs are
SSTL_2, Class II compatible.
The CY2SSTV16859 operates from a differential clock (CLK
and CLK#) of frequency up to 280 MHz. Data are registered at
crossing of CLK going high and CLK# going low.
When RESET# is low, the differential input receivers are
disabled, and undriven (floating) data and clock inputs are
allowed. The LVCMOS RESET# input must always be held at
a valid logic high or low level.
To ensure defined outputs from the register before a stable
clock has been supplied, RESET# must be held in the low
state during power up.
In the DDR DIMM application, RESET# is completely
asynchronous with respect to CLK# and CLK. Therefore, no
timing relationship can be guaranteed between the two. When
entering reset, the register is cleared and the outputs are
driven low quickly, relative to the time to disable the differential
input receivers, thus ensuring no glitches on the output.
However, when coming out of reset, the register becomes
active quickly, relative to the time to enable the differential
input receivers.
Block Diagram
Pin Configuration
RESET #
CLK
CLK #
D1
VREF
D Q1A
C
Q1B
R
To 12 Other Channels
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64 VDDQ
63 GND
62 D13
61 D12
60 VDD
59 VDDQ
58 GND
57 D11
56 D10
55 D9
54 GND
53 D8
52 D7
51 RESET #
50 GND
49 CLK #
48 CLK
47 VDDQ
46 VDD
45 VREF
44 D6
43 GND
42 D5
41 D4
40 D3
39 GND
38 VDDQ
37 VDD
36 D2
35 D1
34 GND
33 VDDQ
64 TSSOP Package
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07463 Rev. *B
Revised July 29, 2003




 CY2SSTV16859
www.DataSheet4U.com
Pin Configuration (continued)
CY2SSTV16859
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
56
1
55
54
53
52
51
50
49 48
47
46
45 44
4342
2 41
3 40
4 39
5 38
6 37
7 36
8 35
9 34
10 33
11 32
12 31
13 30
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
D10
D9
D8
D7
RESET#
GND
CLK#
CLK
VDDQ
VDD
VREF
D6
D5
D4
56 QFN Package
Pin Description
TSSOP
51
7,15,34,39,43,50,54,58,63
37,46,60
6,18,27,33,38,47,59,64
45
Pin
QFN
38
37,48
26,33,45
9,17,23,27,34,44,49,55
32
16,14,13,12,11,10,9,8,5,4,3,2,1 7,6,5,4,3,2,1,56,54,53,52,51,50
32,31,30,29,28,25,24,23,22,21,20, 22,21,20,19,18,16,15,14,13,12
19,17
11,10,8
35,36,40,41,42,44,52,53,55,56,57, 24,25,28,29,30,31,39,40,41,42
61,62
43,46,47
48,49
35,36
Name
Description
RESET#
GND
VDD
VDDQ
VREF
QA(1:13)
QB(1:13)
Disable Clocking and Reset Latch
Ground
Supply Voltage
Supply Voltage, Quiet
Reference Voltage for Data Inputs
D(1:13)
Data Outputs
Data Outputs
D(1:13) Data Inputs
CLK, CLK# Differential Clock Signals
Table 1. Function Table[1,2,3]
RESET#
H
H
H
L
Notes:
1. H = High voltage level.
2. L = Low voltage level.
3. X = Don’t care.
CLK
L or H
X or floating
INPUTS
CLK#
L or H
X or floating
D
L
H
X
X or floating
OUTPUT
Q
L
H
Q0
L
Document #: 38-07463 Rev. *B
Page 2 of 8




 CY2SSTV16859
www.DataSheet4U.com
CY2SSTV16859
Absolute Maximum Conditions[4,5]
Parameter
Description
Condition
VTERM[6]
VTERM[7]
Terminal Voltage with respect to VSS
Terminal Voltage with respect to VSS
TSTG
Storage Temperature
IOUT
DC Output Current
IIK Continuous Clamp Current
VI<0 or VI>VSS
IOK Continuous Clamp Current
VO<0 or VO>VDD
Idd Continuous Current through each VDD, VDDQ or VSS
ISS
Min.
–0.5
–0.5
–65°
–50
–50
–50
–100
Max.
3.6
VDD + 0.5
150°C
50
50
50
100
Unit
V
V
°C
mA
mA
mA
mA
Recommended Operating Conditions[8]
Parameter
Description
Min.
Typ.
Max.
Unit
VDD Supply voltage
2.3 2.5
VDDQ Output supply voltage PC1600,PC2100,PC2700 2.3 2.5
PC3200
2.5 2.6
2.7 V
2.7 V
2.7 V
VREF
Reference voltage
(VREF = VDDQ/2)
PC1600,PC2100,PC2700
PC3200
1.15
1.25
1.25
1.3
1.35 V
1.35 V
VTT Termination voltage
VI Input voltage
VIH AC Data Input high-level voltage
VIL AC Data Input low-level voltage
VIH DC Data Input high-level voltage
VIL DC Data Input low-level voltage
VIH RESET# Input high-level voltage
VIL RESET# Input low-level voltage
VICR CLK, CLK# Common-mode input voltage range
VI(PP) CLK, CLK# Peak-to-peak input voltage
IOH High-level output current
IOL Low-level output current
TA Operating free-air temperature
DC Electrical Specifications
VREF – 40 mV
0
VREF + 310 mV
VREF + 150 mV
1.7
0.97
360
0
VREF
VREF + 40 mV
VDD
VREF – 310 mV
VREF – 150 mV
0.7
1.53
–20
20
85
V
V
V
V
V
V
V
V
V
mV
mA
mA
°C
Parameter Description
Condition
VDD
Min.
Typ.[9] Max. Unit
VIK Clamp Voltage II = –18 mA
2.3V
– – –1.2 V
VOH High level output IOH = –100 µA
voltage
IOH = –16 mA
2.3 to 2.7V VDD – 0.2
2.3V
1.95
–V
–V
VOL Low level output IOL = 100 µA
voltage
IOL = 16 mA
2.3 to 2.7V
2.3
– 0.2 V
– 0.35 V
II
All Inputs
VI = VDD or VSS
2.7V
– – ± 5 µA
IDD Static Standby RESET# = VSS
IO = 0 2.7V
– – 10 µA
Static Operating RESET# = VDD, VI = VIH(AC) or VIL(AC)
2.7 – – 40.0 mA
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Stresses greater than those listed under Absolute Maximum Conditions may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended period may affect reliability.
6. VDD/VDDQ terminals.
7. All terminals except VDD.
8. The RESET# input of the device must be held at VDD or VSS to ensure proper device operation.
9. All typical values are measured at TAMB = 25°C
Document #: 38-07463 Rev. *B
Page 3 of 8



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