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CY2SSTV16859 Dataheets PDF



Part Number CY2SSTV16859
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant
Datasheet CY2SSTV16859 DatasheetCY2SSTV16859 Datasheet (PDF)

www.DataSheet4U.com CY2SSTV16859 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 mA per JESD78, Class II • 64-pin TSSOP/JEDEC and 56-pin QFN package availability • JEDEC specification supported The CY2SSTV16859 operates from a differential .

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www.DataSheet4U.com CY2SSTV16859 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 mA per JESD78, Class II • 64-pin TSSOP/JEDEC and 56-pin QFN package availability • JEDEC specification supported The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. The LVCMOS RESET# input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power up. In the DDR DIMM application, RESET# is completely asynchronous with respect to CLK# and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register is cleared and the outputs are driven low quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. Description This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations. All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input. All outputs are SSTL_2, Class II compatible. Block Diagram Pin Configuration RESET # CLK CLK # D1 D VREF C R Q1B Q1A To 12 Other Channels Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET # GND CLK # CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ 64 TSSOP Package Cypress Semiconductor Corporation Document #: 38-07463 Rev. *B • 3901 North First Street • San Jose, CA 95134 CY2SSTV16859 • 408-943-2600 Revised July 29, 2003 www.DataSheet4U.com CY2SSTV16859 Pin Configuration (continued) VDDQ VDDQ VDDQ Q10A Q11A Q12A Q13A GND VDD Q8A Q9A D13 D12 D11 Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 D10 D9 D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 D5 D4 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 VDDQ VDDQ VDDQ VDD D1 Q7B Q6B Q5B Q4B Q3B Q2B Q1B D2 56 QFN Package Pin Description Pin TSSOP 51 7,15,34,39,43,50,54,58,63 37,46,60 6,18,27,33,38,47,59,64 45 16,14,13,12,11,10,9,8,5,4,3,2,1 38 37,48 26,33,45 9,17,23,27,34,44,49,55 32 7,6,5,4,3,2,1,56,54,53,52,51,50 QFN RESET# GND VDD VDDQ VREF QA(1:13) QB(1:13) D(1:13) Disable Clocking and Reset Latch Ground Supply Voltage Supply Voltage, Quiet Reference Voltage for Data Inputs D(1:13) Data Outputs Data Outputs Data Inputs Name Description 32,31,30,29,28,25,24,23,22,21,20, 22,21,20,19,18,16,15,14,13,12 19,17 11,10,8 35,36,40,41,42,44,52,53,55,56,57, 24,25,28,29,30,31,39,40,41,42 61,62 43,46,47 48,49 Table 1. Function Table RESET# H H H L Notes: 1. H = High voltage level. 2. L = Low voltage level. 3. X = Don’t care. 35,36 [1,2,3] CLK, CLK# Differential Clock Signals INPUTS CLK ↑ ↑ L or H X or floating CLK# ↓ ↓ L or H X or floating D L H X X or floating D3 OUTPUT Q L H Q0 L Document #: 38-07463 Rev. *B Page 2 of 8 www.DataSheet4U.com CY2SSTV16859 Absolute Maximum Conditions[4,5] Parameter VTERM TSTG IOUT IIK IOK Idd ISS [6] Description Terminal Voltage with respect to VSS Terminal Voltage with respect to VSS Storage Temperature DC Output Current Continuous Clamp Current Continuous Clamp Current Continuous Current through each VDD, VDDQ or VSS Condition Min. –0.5 –0.5 –65° –50 Max. 3.6 VDD + 0.5 150°C 50 50 50 100 Unit V V °C mA mA mA mA VTERM[7] VI<0 or VI>VSS VO<0 or VO>VDD –50 –50 –100 Recommended Operating Conditions[8] Parameter VDD VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VI(PP) IOH IOL TA Parameter VIK VOH VOL II IDD Supply voltage Output supply voltage PC1600,PC2100,PC2700 PC3200 Reference voltage (VREF = VDDQ/2) Termination voltage Input voltage AC Data Input high-level voltage AC Data Input low-level voltage DC Data Input high-level voltage DC Data Input low-level voltage RESET# Input high-level voltage RESET# Input low-level voltage CLK, CLK# Common-mode input voltage range CLK, CLK# Peak-to-peak input voltage High-level output current Low-level output current Operating free-air temperature PC1600,PC2100,PC2700 PC3200.


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