DatasheetsPDF.com

STA120 Dataheets PDF



Part Number STA120
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description DIGITAL AUDIO INTERFACE RECEIVER
Datasheet STA120 DatasheetSTA120 Datasheet (PDF)

www.DataSheet4U.com STA120 DIGITAL AUDIO INTERFACE RECEIVER s s s s s MONOLITHIC CMOS RECEIVER 3.3V SUPPLY VOLTAGE LOW-JITTER, ON-CHIP CLOCK RECOVERY 256xFs OUTPUT CLOCK PROVIDED SUPPORTS: AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 PROFESSIONAL AND CONSUMER FORMATS EXTENSIVE ERROR REPORTING REPEAT LAST SAMPLE ON ERROR OPTION SO28 ORDERING NUMBER: STA120D DESCRIPTION The STA120 is a monolithic CMOS device that receives and decodes audio data according to the AES/EBU, IEC 958, S/PDIF, & EIA.

  STA120   STA120


Document
www.DataSheet4U.com STA120 DIGITAL AUDIO INTERFACE RECEIVER s s s s s MONOLITHIC CMOS RECEIVER 3.3V SUPPLY VOLTAGE LOW-JITTER, ON-CHIP CLOCK RECOVERY 256xFs OUTPUT CLOCK PROVIDED SUPPORTS: AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 PROFESSIONAL AND CONSUMER FORMATS EXTENSIVE ERROR REPORTING REPEAT LAST SAMPLE ON ERROR OPTION SO28 ORDERING NUMBER: STA120D DESCRIPTION The STA120 is a monolithic CMOS device that receives and decodes audio data according to the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340/1201 interface standards. The STA120 recovers the clock and synchronizaBLOCK DIAGRAM tion signals and de-multiplexes the audio and digital data. Differential or single ended inputs can be decoded. The STA120 de-multiplexes the channel, user and validity data directly to serial output pins with dedicated output pins for the most important channel status bits. VD+ 7 DGND 8 VA+ 22 FILT 20 AGND MCK 21 19 M3 17 M2 18 M1 24 M0 23 26 9 RS422 Receiver CLOCK & DATA RECOVERY DE MUX AUDIO SERIAL PORT 12 11 SDATA SCK FSYNC RXP RXN 10 1 REGISTERS 14 28 C U VREF MUX MUX 13 CS12/FCK 16 SEL 6 5 4 3 2 27 25 ERF 15 CBL D97AU613A C0/E0 Ca/E1 Cb/E2 Cc/F0 Cd/F1 Ce/F2 December 2002 1/15 www.DataSheet4U.com STA120 ABSOLUTE MAXIMUM RATINGS Symbol VD+, VA+ VIN Tamb Tstg Power Supply Voltage Input Voltage ( excluding pins 9, 10) Ambient Operating Temperature (power applied) Storage Temperature Parameter Value 4 -0.3 to VD+ +0.3 -30 to +85 -40 to 150 Unit V V °C °C PIN CONNECTIONS (Top view) C Cd/F1 Cc/F0 Cb/E2 Ca/E1 C0/E0 VD+ DGND RXP RXN FSYNC SCK CS12/FCK U 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D97AU609A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VERF Ce/F2 SDATA ERF M1 M0 VA+ AGND FILT MCK M2 M3 SEL CBL PINS DESCRIPTION N. 7 8 21 22 11 12 Name VD+ DGND AGND VA+ FSYNC SCK Description Positive Digital Power.Positive supply for the digital section. Nominally 3.3V. Digital Ground.Ground for the digital section. Analog Ground.Ground for the analog section. AGND should be connected to same ground as DGND. Positive Analog Power.Positive supply for the analog section. Nominally 3.3V. Frame Sync.Delineates the serial data and may indicate the particular channel, left or right and may be an input or output. The format is based on M0, M1, M2 and M3 pins. Serial Clock.Serial clock for SDATA pin which can be configured (via the M0, M1, M2 and M3 pins) as an input or output and can sample data on the rising or falling edge. As an output, SCK will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must be provided in all normal modes. Serial Port Mode Selects.Selects the format of Fsync and the sample edge of SCK with respect to SDATA. Serial Data. Audio data serial output pin. Power Supply Audio Output Interface 17, 18, 23, 24 26 M2, M3, M1, M0 SDATA 2/15 www.DataSheet4U.com STA120 PINS DESCRIPTION (continued) N. 1 Name C Description Channel Status Output. Received channel status bit serial output port. FSYNC may be used to latch this bit externally. Except in I2S modes when this pin is updated at the active edge off Fsync. Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is high. Channel status information is displayed for the channel selected by CS12. C0, which is channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL. Frequency reporting Bits.Encoder sample frequency information that is enabled by bringing SEL low. A proper clock on FCK must be input for at least two thirds of a channel status block for these pins to be valid. They are updated three times per block, starting at the block boundary. Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is high. Channel status information is displayed for the channel selected by CS12. C0, which is channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL. Frequency reporting Bits.Encoded sample frequency information that is enabled by bringing SEL low. A proper clock on FCK must be input for at least two thirds of a channel status block for these pins to be valid. They are updated three times per block, starting at the block boundary. Channel Status Output Bits.These pin are dual Function with the "C" bits selected when SEL is high. Channel status information is displayed for the channel selected by CS12. C0, which is channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL. Error Condition.Encoded error information that is enabled by bringing SEL low. The error codes are prioritized and latched so that the error code displayed is the highest level of error since the l.


STA1050 STA120 STA124


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)