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ML145145 Dataheets PDF



Part Number ML145145
Manufacturers LANSDALE Semiconductor
Logo LANSDALE Semiconductor
Description 4-Bit Data Bus Input PLL Frequency Synthesizer
Datasheet ML145145 DatasheetML145145 Datasheet (PDF)

www.DataSheet4U.com ML145145 4–Bit Data Bus Input PLL Frequency Synthesizer INTERFACES WITH SINGLE–MODULUS PRESCALERS Legacy Device: Motorola MC145145-2 The ML145145 is programmed by a 4–bit input, with strobe and address lines. The device features consist of a reference oscillator, 12–bit programmable reference divider, digital phase detector, 14–bit programmable divide–by–N counter, and the necessary latch circuitry for accepting the 4–bit input data. • Operating Temperature Range: TA – 40 t.

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www.DataSheet4U.com ML145145 4–Bit Data Bus Input PLL Frequency Synthesizer INTERFACES WITH SINGLE–MODULUS PRESCALERS Legacy Device: Motorola MC145145-2 The ML145145 is programmed by a 4–bit input, with strobe and address lines. The device features consist of a reference oscillator, 12–bit programmable reference divider, digital phase detector, 14–bit programmable divide–by–N counter, and the necessary latch circuitry for accepting the 4–bit input data. • Operating Temperature Range: TA – 40 to 85°C • Low Power Consumption Through the Use of CMOS Technology • 3.0 to 9.0 V Supply Range • Single Modulus 4–Bit Data Bus Programming • ÷N Range = 3 to 16,383, ÷R Range = 3 to 4,095 • “Linearized” Digital Phase Detector Enhances Transfer Function Linearity • Two Error Signal Options: Single–Ended (Three–State) Double–Ended P DIP 18 = VP PLASTIC DIP CASE 707 18 1 20 SOG 20 = -6P SOG PACKAGE CASE 751D 1 CROSS REFERENCE/ORDERING INFORMATION MOTOROLA LANSDALE PACKAGE P DIP 18 MC145145P1 ML145145VP SOG 20 MC145145DW2 ML145145-6P Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE. PIN ASSIGNMENTS PLASTIC DIP D1 D0 fin 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 D2 D3 REFout φR φV LD PDout ST A2 BLOCK DIAGRAM REFout VSS VDD OSCin OSCout OSCin OSCout 12–BIT R COUNTER LATCH 4 LATCH 5 LATCH 6 LOCK DETECT LD A0 A1 SOG PACKAGE D1 D0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D2 D3 REFout φR φV LD PDout ST A2 NC D0 D1 D2 D3 A0 A1 A2 ST fR LATCH CONTROL CIRCUITRY fV LATCHES PHASE DETECTOR A PDout NC fin VSS VDD LATCH 0 fin LATCH 1 LATCH 2 L3 PHASE DETECTOR B φV φR OSCin OSCout A0 A1 14–BIT N COUNTER NC = NO CONNECTION Page 1 of 12 www.lansdale.com Issue b B ML145145 www.DataSheet4U.com LANSDALE Semiconductor, Inc. Page 2 of 12 www.lansdale.com Issue b ML145145 www.DataSheet4U.com LANSDALE Semiconductor, Inc. Page 3 of 12 www.lansdale.com Issue b ML145145 www.DataSheet4U.com LANSDALE Semiconductor, Inc. Page 4 of 12 www.lansdale.com Issue b ML145145 www.DataSheet4U.com LANSDALE Semiconductor, Inc. Page 5 of 12 www.lansdale.com Issue b ML145145 www.DataSheet4U.com LANSDALE Semiconductor, Inc. PIN DESCRIPTIONS INPUT PINS D0 – D3 Data Inputs (PDIP – Pins 2, 1, 18, 17; SOG – Pins 2, 1, 20, 19) Information at these inputs is transferred to the internal latches when the ST input is in the high state. D3 is most signigicant bit. f in Frequency Input (PDIP – Pin 3, SOG – Pin 4) Input to ÷N portion of synthesizer. f in is typically derived from the loop VCO and is ac couples. For larger amplitude signals (standard CMOS – logic levels) dc coupling may be used. OSCin/OSCout Reference Oscillator Input/Output (PDIP – Pins 6, 7; SOG – Pins 7, 8) These pins form an on–chip reference oscillator when connected to terminals of an external parallel resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSCin to ground and OSCout to ground. OSCin may also serve as input for an externally–generated reference signal. This signal is typically AC coupled to OSCin but for larger amplitude signals (standard CMOS–logic levels) DC coupling may also be used. In the external refrence mode, no connection is required to OSCout. A0 – A2 Address Inputs (PDIP – Pins 8, 9, 10; SOG – Pins 9, 10, 12) A0, A1 and A2 are used to define which latch receives the information on the data input lines. The addresses refer to the following latches: latch, the falling edge of strobe latches data into the latch. This pin should normally be held low to avoid loading latches with invalid data. OUTPUT PINS PDout Single–Ended Phase Detector output (PDIP – Pin 12, SOG – Pin 14) Three–state output of phase detector for use as loop–error signal. Frequency fV > fR or fV Leading: Negative Pulses Frequency fV < fR or fV Lagging: Positive Pulses Frequency fV = fR and Phase Coincidence: High–Impedance State LD Lock Detector Signal (PDIP – Pin 13, SOG – Pin 15) High level when loop is locked (fR, fV of same phase and frequency). Pulses low when loop is out of lock. φV, φR Phase Detect or Outputs (PDIP – Pin 12, SOG – Pin 14) These phase detector outputs can be combined externally for a loop–error signal. A single–ended output is also available for this purpose (see PDout). If frequency fV is greater than fR or if the phase of fV is leading, then error information is provided by φV pulsing low. φR remains essentially high. If the frequency of fV – fR and both are in phase, then both φV and φR remain high except for a small minimum time period when both pulse low in phase. REFout Buffered Reference Output (DIP – Pin 16, SOG – Pin 18) Buffered output of on–chip reference oscillator or externally provided reference–input signal. POWER SUPPLY PINS VSS Ground (PDIP – Pin 4, SOG – Pin 5) Circuit Ground VDD Positive Power Supply (PDIP – Pin 5, SOG – Pin 6) The positive supply voltage may range from 3.0 to 9.0 V with respect t.


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