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10 Gbit/s Transmitter MUX with Re-timing GD16585
Preliminary
General Description
GD16585 is a 9.95328 Gbit/s transmitter chip for use in SDH STM-64 and SONET OC-192 optical communication systems. GD16585 integrates all the main functions of the transmitter, which is clock generation, PLL circuits and multiplexer in a single monolithic IC. Hence only an external loop filter and a VCXO are required. The main functions of GD16585 are shown in the figure below. The clock generation is made on-chip by a low noise and tuneable 10 GHz VCO. The VCO frequency is controlled by the PLL with an external loop filter, allowing the user to control the loop characteristic. The clock synchronisation is controlled by the Phase and Frequency Detector with a 155 MHz or 622 MHz reference clock input. GD16585 multiplexes a 16 bit parallel 622 Mbit/s interface into a serial 9.9553 Gbit/s data stream. The timing between the input data and the on-chip clock system are controlled by a second Phase and Frequency Detector (PFCX). It compares the input data clock with the on-chip load clock. The output of the PFCX is the phase and frequency control of the external VCXO reference clock. The output of the MUX stage is retimed by the 10 GHz clock and the output driver is a Current Mode Logic (CML) output with internal 50 Ω termination resistors. The 16 bit wide parallel input interface is LVDS compatible with a 2 × 50 Ω internal load termination. GD16585 is manufactured in a Silicon Bipolar process. GD16585 uses a -5.2 V supply voltage and +3.3 V supply for interfacing LVDS. The power dissipation is 2.2 W, typical. GD16585 is delivered in an 132 leads ceramic Ball Grid Array (BGA). The size of the package is 13 × 13 mm.
Features
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On-chip low noise VCO with a wide tuning range. Automated capture of the VCO frequency by a true phase and frequency detector. Retiming of MUX stage output with 10 GHz clock. Clock failure detection NLDET. Phase nulling circuit for easy interfacing with the system ASIC. 16:1 MUX with differential 622 Mbit/s LVDS data inputs. CML data input with 50 Ω internal load termination. LVDS compatible data and clock inputs with 100 Ω internal load termination. 622 MHz clock output for counter clocking. 155 MHz or 622 MHz reference clock input (selectable). Dual supply operation: -5.2 V and +3.3 V Low power dissipation: 2.2 W (typ.). Silicon Bipolar process. 132 leads ceramic BGA 13 × 13 mm package. Available in two versions: – GD16585 for 10 Gbit/s – GD16589 for 10.66 Gbit/s
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DI0 DIN0 Parallel Input Data DI15 DIN15 NLDET VCUR OUT OUTN
FF
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16:1 Multiplexer
SEL1 SEL2 CKOUT CKOUTN CKI CKIN
Phase Selector
Timing Control
Phase Frequency Detector
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PCTL
PFCX VCO
PHIGH PLOW
Applications
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TCK
Telecommunication systems: – SDH STM-64 – SONET OC-192. Fibre optic test equipment.
Data Sheet Rev. 04
PCTLX
SGNX
VCTL
SEL3
REFCK/N VCC VDD VDDO VDDA VEE
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Functional Details
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