Pair Interface. MC68833 Datasheet

MC68833 Interface. Datasheet pdf. Equivalent

Part MC68833
Description Twisted Pair Interface
Feature MOTOROLA www.DataSheet4U.com SEMICONDUCTOR TECHNICAL DATA Order this data sheet from Logic Marketi.
Manufacture Motorola
Datasheet
Download MC68833 Datasheet



MC68833
www.DMatOaSTheOet4RUO.coLmA
SEMICONDUCTOR TECHNICAL DATA
Order this data sheet
from Logic Marketing
Product Preview
Twisted Pair Interface
for 100Base-TX Local Area Networks
Overview
100Base–TX is a LAN standard under IEEE auspices. The twisted pair
cable connecting two stations can be up to 100 meters in length. Users
are encouraged to refer to the pertinent IEEE 802.3 standard documents
for further information.
Introduction
The MC68833 Twisted Pair Interface Chip (TPIC) is a transceiver
capable of transmitting and receiving MLT3 encoded datastreams, as well
as handling clock and data recovery. The TPIC implements the lower
portion of the physical layer (PHY) functions of the Fast Ethernet
standard and, with its Auto Negotiation Fast Link Pulse “Pass Through”
capability, is well suited for 100Base–TX applications. It performs a
five–bit parallel to serial conversion during transmission, as well as a
five–bit serial to parallel conversion during reception.
MC68833
FA SUFFIX
TQFP PACKAGE
CASE 931–02
MC68833 Features
Supports Twisted Pair Media
Supports MLT–3 Line Code
Selectable Auto Negotiation mode has FLP and NLP “Pass–Through” Capability
Controlled Twisted Pair Output Transition Times May Eliminate Need for Transmit Filter
Adaptive Receive Equalization supports TP line lengths of 0 to 100 meters
TP Receiver Includes Circuitry Which Enables Error Free Reception of Data Distorted with Base Line Wander
Twisted Pair (TP) Transceiver Complies with ANSI X3T9.5 TP–PMD Standard and the IEEE 802.3 100Base–TX Ethernet
Draft Standard
Meets Jitter Requirements of ANSI X3T9.5 TP–PMD
Physical Layer Support for Fast Ethernet
Digital Phase–Locked Loop (DPLL) Provides Run Length Immunity
Transmit Off Capability for True Quiet Line State
Uses a 25 Mhz External Frequency Reference
Converts Received Serial Bit Stream to Five–Bit Parallel Form
Recovers 125 Mhz Clock from Incoming Serial MLT3 Data Stream
Generates 25 Mhz Receive Clock
Small Number of Passive External Components Required
Selectable Low Power Mode
Loop Back Capability
Single +5V Power Supply
Utilizes 0.8uM BiCMOS Technology
10mM X 10mM, 64 Pin, TQFP Package (Power Enhanced Leadframe Package)
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
4/95
© Motorola, Inc. 1995
REV 0



MC68833
www.DMataCS6he8e8t43U3.com
Functional Description
100Base–T MAC with 802.3u PCS PHY Capability
(Can also have full Auto–Negotiation capability)
MC68833
SD
RDATA [4] (rFLP)
RDATA [3:0]
RSCLK
AUTONG
TDATA [3:0]
TDATA [4] (tFLP)
SD
RDATA [4] (rFLP)
RDATA [3:0]
RSCLK
AUTONG
TDATA [3:0]
TDATA [4] (tFLP)
TDH
TDL
RDH
RDL
MAGNETICS
AND
CONNECTOR
Figure 1. Simplified Block Diagram for Twisted Pair Applications of the MC68833 TPIC
RSCLK
RDATA [4:0]
100Base–T PCS PHY or MAC INTERFACE
SD TDIS LB
AUTONG TDATA [4:0]
MC68833 INTERFACE LOGIC
TCLKIN
AWAKE
FREQ
MULT
SYSTEM
MGT
RECEIVER
SERIAL TO
PARALLEL
CONVERSION
NRZI to NRZ
DECODER
DPLL
TP INPUT
MLT3 to NRZI
AUTO–
EQUALIZATION
SQUELCH
TRANSMITTER
PARALLEL
TO SERIAL
CONVERSION
NRZ to NRZI
DECODER
TPTSLRT
TP OUTPUT
NRZI to MLT3
WAVE SHAPING
DRIVER
RDH/L
MEDIA INTERFACE
TDH/L
Figure 2. MC68833 Simplified Block Diagram
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — REV 4





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)