MCP Memory. KAG00J007M-FGG2 Datasheet

KAG00J007M-FGG2 Memory. Datasheet pdf. Equivalent

KAG00J007M-FGG2 Datasheet
Recommendation KAG00J007M-FGG2 Datasheet
Part KAG00J007M-FGG2
Description MCP Memory
Feature KAG00J007M-FGG2; www.DataSheet4U.com KAG00J007M-FGG2 Advance Preliminary MCP MEMORY MCP Specification of 256Mb NAN.
Manufacture Samsung Electronics
Datasheet
Download KAG00J007M-FGG2 Datasheet




Samsung Electronics KAG00J007M-FGG2
www.DataSheet4U.com
KAG00J007M-FGG2
PrelAimdvinanacrye
MCP MEMORY
MCP Specification of
256Mb NAND*2 and 256Mb Mobile SDRAM
- 1 - Revision 0.6
October 2003



Samsung Electronics KAG00J007M-FGG2
www.DataSheet4U.com
KAG00J007M-FGG2
PrelAimdvinanacrye
MCP MEMORY
Document Title
Multi-Chip Package MEMORY
256M Bit(32Mx8) Nand Flash*2 / 256M Bit(4Mx16x4Banks) Mobile SDRAM
Revision History
Revision No. History
0.0 Initial issue.
(512M NAND DDP C-Die_ Ver 1.0)
( 256M MSDRAM E‘-Die_Ver 0.5)
Draft Date
Remark
March 25, 2003 Advance
0.5 - Added Column address : page 37
- Changed the values of Icc
- Inserted Commercial Temperature
- Inserted DS 1/4 & 1/8 option in EMRS table.
- Changed default DS from full size to half size.
- Changed the comment related with tRDL & tDAL : page 35
- Corrected errata from tRC to tARFC in the table : page 33
- Corrected errata from tSRFC to tSRFX : page 45
- Corrected MRS table : page 38
June 3 , 2003 Preliminary
0.6 <Common>
- Changed the MSDRAM speed code of the MCP part number
from "X"(66MHz) to "2"(105MHz)
October 13 , 2003 Preliminary
<NAND Flash> .... ver 2.6
- Corrected functional block diagram : page 6
- Changed the maximum operation current : page 10
Read : Icc1 30mA --> 20mA
Program : Icc2 40mA --> 20mA
Erase : Icc3 40mA --> 20mA
- Added new definition of the number of invalid blocks : page 11
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
<Mobile SDRAM> .... ver 0.6
- Changed the value of tss : page 36
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
- 2 - Revision 0.6
October 2003



Samsung Electronics KAG00J007M-FGG2
www.DataSheet4U.com
KAG00J007M-FGG2
PrelAimdvinanacrye
MCP MEMORY
Multi-Chip Package MEMORY
256M Bit (32Mx8) Nand Flash*2 / 256M Bit (4Mx16x4Banks) Mobile SDRAM
FEATURES
<Common>
Operating Temperature : -25°C ~ 85°C
Package : 107-ball FBGA Type - 10.5x13mm, 0.8mm pitch
<NAND>
Power Supply Voltage : 2.4~2.9V
Organization
- Memory Cell Array : (64M + 2048K)bit x 8bit
- Data Register : (512 + 16)bit x 8bit
Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
Page Read Operation
- Page Size : (512 + 16)Byte
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Intelligent Copy-Back
Unique ID for Copyright Protection
<SDRAM>
Power Supply Voltage : 1.65~1.95V
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
GENERAL DESCRIPTION
The KAG00J007M is a Multi Chip Package Memory which combines 512Mbit Nand Flash Memory(organized with two pieces of
256Mbit Nand Flash Memory) and 256Mbit synchronous high data rate Dynamic RAM.
512Mbit NAND Flash memory is organized as 64M x8 bits and 256Mbit SDRAM is organized as 4M x16 bits x4 banks.
In 512Mbit NAND Flash, a 528-byte page program can be typically achieved within 200us and an 16K-byte block erase can be typi-
cally achieved within 2ms. In serial read operation, a byte can be read by 50ns. IO pins serve as the ports for address and data input/
output as well as command inputs. Even the write-intensive systems can take advantage of flashs extended reliability of 100K pro-
gram/erase cycles with real time mapping-out algorithm. These algorithms have been implemented in many mass storage applica-
tions.
In 256Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
The KAG00J007M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 107-ball FBGA Type.
- 3 - Revision 0.6
October 2003







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)