GD16588

www.DataSheet4U.com an Intel company 10 Gbit/s Receiver, CDR and DeMUX GD16584/GD16588 (FEC) Preliminary General Description GD16584 and GD16588 are Receiver chips for use in STM-64/192 and Optical Transport Networking (OTN) systems. The component is available in two versions: u GD16584 for 9.5328 Gbit/s. u GD16588 for 10.66 Gbit/s for OTN or Forward Error Correction (FEC). Except the different operating bit rates the two versions are functional identical. The receiver is a Clock and Data Recovery IC with: u a low noise VCO u a Bang-Bang Phase Detector u a 1:16 De-multiplexer u a Lock Detect u a Phase and Frequency Detector. Clock and data are regenerated by using a Phase Locked Loop (PLL) with an external passive loop filter. The VCO frequency is controlled by one of the two Phase Detectors in order to ensure capture and lock to the line data rate. The Lock Detector circuit monitors the VCO frequency and determines when the VCO is within the lock range. When the frequency deviates more than VCO VCTL Timing Control Features 500 ppm from the reference clock, it automatically switches the phase and frequency detector into the PLL loop. In the auto lock mode the locking range is selectable between 500 or 2000 ppm. When the VCO frequency is within the lock range, the Bang-Bang Phase Detector takes over. It controls the phase of the VCO until the sampling point of data is in the middle of the bit period, where the eye opening is largest. A ±40 mV Decision Threshold Control (DT...