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87C196KR KQ 87C196JV JT 87C196JR JQ ADVANCED 16-BIT CHMOS MICROCONTROLLER
Automotive
Y Y Y Y
b 40 C to a 125 C Ambient
Y
High Performance CHMOS 16-Bit CPU Up to 48 Kbytes of On-Chip EPROM Up to 1 5 Kbytes of On-Chip Register RAM Up to 512 Bytes of Additional RAM (Code RAM) Register-Register Architecture Up to 8 Channel 10-Bit A D with Sample Hold Up to 37 Prioritized Interrupt Sources Up to Seven 8-Bit (56) I O Ports Full Duplex Serial I O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port
Device Pins Package 68-pin PLCC 68-pin PLCC 52-pin PLCC 52-pin PLCC 52-pin PLCC 52-pin PLCC EPROM 16K 12K 48K 32K 16K 12K Reg RAM 488 360 1 5K 1 0K 488 360
Y Y Y
High Speed Peripheral Transaction Server (PTS) Two 16-Bit Software Timers 10 High Speed Capture Compare (EPA) Full Duplex Synchronous Serial I O Port (SSIO) Two Flexible 16-Bit Timer Counters Quadrature Counting Inputs Flexible 8- 16-Bit External Bus Programmable Bus (HLD HLDA) 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide 68-Pin and 52-Pin PLCC Packages
Y
Y Y Y Y Y Y Y
Y Y
Y Y Y Y Y
Code RAM 256 128 512 512 256 128
I O 56 56 41 41 41 41
EPA 10 10 6 6 6 6
SIO Y Y Y Y Y Y
SSIO Y Y Y Y Y Y
A D 8 8 6 6 6 6
87C196KR 87C196KQ 87C196JV 87C196JT 87C196JR 87C196JQ
The 87C196KR KQ JV JT JR JQ devices represent the fourth generation of MCS 96 Microcontroller products implemented on Intel’s advanced 1 micron process technology These products are based on the 80C196KB device with improvements for automotive applications The instruction set is a true super set of 80C196KB The 87C196JR is a 52-pin version of the 87C196KR device while the 87C196KQ JQ are memory scalars of the 87C196KR JR The 87C196JV JT A-step devices (JV-A JT-A) are the newest members of the MCS 96 microcontroller family These devices are memory scalars of the 87C196JR D-step (JR-D) and are designed for strict functional and electrical compatibility The JT-A has 32 Kbytes of on-chip EPROM 1 0 Kbytes of Register RAM and 512 bytes of Code RAM The JV-A has 48 Kbytes of on-chip EPROM 1 5 Kbytes of Register RAM and 512 bytes of Code RAM
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
November 1995
Order Number 270827-006
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87C196KR KQ 87C196JV JT 87C196JR JQ
The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU The 87C196Kx Jx family members listed above are composed of the high-speed (16 MHz) core as well as the following peripherals up to 48 Kbytes of Programmable EPROM up to 1 5 Kbytes of Register RAM 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space an eight channel-10-Bit g 3 LSB analog to digital converter with programmable S H times with conversion times k 5 ms at 16 MHz an asynchronous synchronous serial I O port (8096 compatible) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port (8096 compatible) with a dedicated 16-bit baud rate generator an additional synchronous serial I O port with full duplex master slave transceivers a flexible timer counter structure with prescaler cascading and quadrature capabilities 10 modularized multiplexed high speed I O for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS) The PTS has several channel modes including single burst block transfers from any memory location to any memory location a PWM and PWM toggle mode to be used in conjunction with the EPA and an A D scan mode Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area Please refer to the following datasheets for higher frequency versions of devices contained within this datasheet 20 MHz 87C196JT Order 272529 20 MHz 87C196JV Order Number 272580
Up to 37 Interrupt Vectors Up to 512 Bytes of Code RAM Up to 1 5 Kbytes of Register RAM
‘‘Windowing’’ Allows 8-Bit Addressing to Some 16-Bit Addresses 1 75 ms 16 x 16 Multiply 3 ms 32 16 Divide
Oscillator Fail Detect
PERIPHERAL FEATURES
Programmable A D Conversion and S H Times 10 Capture Compare I O with 2 Flexible Timers Synchronous Serial I O Port for Full Duplex Serial I O
Total Utilization of ALL Available Pins (I O Mux’d
with Control)
2 16-Bit Timers with Prescale Cascading and
Quadrature Counting Capabilities
Up to 12 Externally Trig.