FLASH+: The End of the Emulation Compromise
Designers are constantly under pressure to reduce the size of printed circuit boards, and are frequently
faced with the EEPROM emulation dilemma: in a system that requires both Flash and EEPROM memory
functions, is it necessary to use separate EEPROM and Flash memory chips? In theory the answer is ‘no’
because with appropriate software part of the Flash memory can be made to emulate an EEPROM. in
practice, however, the benefits of this approach are often outweighed by severe performance penalties.
www.DataSAhneeet4xUc.ictoinmg new memory concept promises to end this dilemma once and for all by allowing EEPROM
functionality to be selectively added to a Flash memory array - a major breakthrough as the Flash cell
structure is much more cost-effective than conventional EEPROM technology. STMicroelectronics has ful-
ly industrialised the concept, and manufactures products that combine 2, 4 or 8 Mbit of Flash memory and
64 or 256 Kbit of EEPROM on the same chip.
The new memory concept is called FLASH+. Using essentially the same process that is used for standard
Flash memories, FLASH+ allows a hardware emulation of the EEPROM function to be performed. This
uses a double metal process that is only a little more complex than the standard single metal EEPROM
process, but allows much smaller cell sizes to be used. However, the benefits of FLASH+ go much further
because the EEPROM functionality can be selectively implemented on the die, resulting in a device that
combines a conventional Flash memory and a full-featured EEPROM on the same chip.
Before this breakthrough, designers who needed Flash and EEPROM in their systems either had to ac-
cept the cost and space overheads of using two separate devices or had to use a software emulation tech-
nique to simulate the EEPROM in a Flash memory.
The software emulation technique was developed to get round the fact that a Flash cell can only be pro-
grammed once between sector-erase cycles. If the application stored parameters and variables in fixed
Flash locations, the Flash sector would have to be erased every time a variable changed value - and with
sector erase times being typically more than one second, this would slow down performance intolerably.
The solution was to write each new parameter value in a fresh Flash location and to maintain a string of
address pointers to allow the latest value to be found. When the sector is full, the latest values are copied
across to a second sector, and the first sector is erased ready to start the process again.
This approach is very straightforward, but the first software emulations to adopt this approach suffered
from the major disadvantage that the microprocessor could not read its program code from the Flash
memory while a sector was being erased. Amongst other effects, this gave a worst-case interrupt re-
sponse time of over a second. Newer Flash architectures such as “Fast Suspend to Read” and “Simulta-
neous Read/Write” have greatly reduced the interrupt latency problem, but still cannot address the most
important disadvantage of software emulation, which is the large and unpredictable access time and the
corresponding increase in power consumption.
REMOVING THE LONG AND UNPREDICTABLE ACCESS TIMES
When the processor wants to access a parameter stored in “simulated EEPROM”, it has to begin at the
initial location and follow the chain of address pointers, tracing through every updated value until it reaches
the current one (the one most recently written). Depending on the number of parameters, and the average