GS8322Z18

GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) 119, 165 & 209 BGA Commercial Temp Industrial Temp Features NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs 2.5 V or 3.3 V +10%/–10% core power supply 2.5 V or 3.3 V I/O supply www.DataSheet4U.com User-configurable Pipeline and Flow Through mode ZQ mode pin for user-selectable high/low output drive IEEE 1149.1 JTAG-compatible Boundary Scan LBO pin for Linear or Interleave Burst mode Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices Byte write operation (9-bit Bytes) 3 chip enable signals for easy depth expansion ZZ Pin for automatic power-down JEDEC-standard 119-, 165- or 209-Bump BGA package 36Mb Pipelined and Flow Through Synchronous NBT SRAM 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by ...