HOTLink Transceiver. CYV15G0101DXB Datasheet

CYV15G0101DXB Transceiver. Datasheet pdf. Equivalent

Part CYV15G0101DXB
Description Single-channel HOTLink Transceiver
Feature CYP15G0101DXB CYV15G0101DXB Single-channel HOTLink II™ Transceiver Single-channel HOTLink II™ Trans.
Manufacture Cypress Semiconductor
Datasheet
Download CYV15G0101DXB Datasheet



CYV15G0101DXB
CYP15G0101DXB
CYV15G0101DXB
Single-channel HOTLink II™ Transceiver
Single-channel HOTLink II™ Transceiver
Features
Second-generation HOTLink® technology
Compliant to multiple standards
ESCON®, DVB-ASI, fibre channel and gigabit ethernet
(IEEE802.3z)
CPRI™ compliant
CYV15G0101DXB compliant to SMPTE 259M and SMPTE
292M
8B/10B encoded or 10-bit unencoded data
Single-channel transceiver operates from 195 to 1500 MBaud
serial data rate
Selectable parity check/generate
Selectable input clocking options
Selectable output clocking options
MultiFrame™ Receive Framer
Bit and byte alignment
Comma or full K28.5 detect
Single- or multi-byte framer for byte alignment
Low-latency option
Synchronous LVTTL parallel input and parallel output interface
Internal phase-locked loops (PLLs) with no external PLL
components
Dual differential PECL-compatible serial inputs
Internal DC-restoration
Dual differential PECL-compatible serial outputs
Source matched for driving 50 transmission lines
No external bias resistors required
Signaling-rate controlled edge-rates
Optional elasticity buffer in receive path
Optional phase align buffer in transmit path
Compatible with
Fiber-optic modules
Copper cables
Circuit board traces
JTAG boundary scan
Built-in self-test (BIST) for at-speed link testing
Per-channel link quality indicator
Analog signal detect
Digital signal detect
Low power 1.25 W at 3.3 V typical
Single 3.3 V supply
100-ball BGA
Pb-free package option available
0.25 µ BiCMOS technology
Functional Description
The CYP15G0101DXB[1] single-channel HOTLink II™
transceiver is a point-to-point communications building block
allowing the transfer of data over a high-speed serial link (optical
fiber, balanced, and unbalanced copper transmission lines) at
signaling speeds ranging from 195 to 1500 MBaud.
The transmit channel accepts parallel characters in an input
register, encodes each character for transport, and converts it to
serial data. The receive channel accepts serial data and converts
it to parallel data, frames the data to character boundaries,
decodes the framed characters into data and special characters,
and presents these characters to an output register. Figure 1
illustrates typical connections between independent host
systems and corresponding CYP(V)15G0101DXB parts. As a
second-generation HOTLink device, the CYP(V)15G0101DXB
extends the HOTLink II family with enhanced levels of
integration and faster data rates, while maintaining serial-link
compatibility (data, command, and BIST) with other HOTLink
devices.
Figure 1. HOTLink II System Connections
10
10
Serial Link
Backplane or Cabled
Connections
10
10
Note
1. CYV15G0101DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYP15G0101DXB refers to devices not compliant to SMPTE 259M and SMPTE
292M pathological test requirements. CYP(V)15G0101DXB refers both devices.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-02031 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2017



CYV15G0101DXB
CYP15G0101DXB
CYV15G0101DXB
The CYV15G0101DXB satisfies the SMPTE 259M and SMPTE
292M compliance as per the EG34-1999 pathological test
requirements. The transmit (TX) section of the
CYP(V)15G0101DXB single-channel HOTLink II consists of a
byte-wide channel. The channel can accept either eight-bit data
characters or pre-encoded 10-bit transmission characters. Data
characters are passed from the transmit input register to an
embedded 8B/10B encoder to improve their serial transmission
characteristics. These encoded characters are then serialized
and output from dual positive ECL (PECL)-compatible
differential transmission-line drivers at a bit-rate of either 10 or
20 times the input reference clock.
The receive (RX) section of the CYP(V)15G0101DXB
single-channel HOTLink II consists of a byte-wide channel. The
channel accepts a serial bit-stream from one of two
PECL-compatible differential line receivers and, using a
completely integrated PLL clock synchronizer, recovers the
timing information necessary for data reconstruction. The
recovered bit-stream is deserialized and framed into characters,
8B/10B decoded, and checked for transmission errors.
Recovered decoded characters are then written to an internal
elasticity buffer, and presented to the destination host system.
The integrated 8B/10B encoder/decoder may be bypassed for
systems that present externally encoded or scrambled data at
the parallel interface.
The parallel I/O interface may be configured for numerous forms
of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path interfaces
from one or multiple sources, the receive interface may be
configured to present data relative to a recovered clock or to a
local reference clock.
The transmit and the receive channels contain BIST pattern
generators and checkers, respectively. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
both transmit and receive sections, as well as across the
interconnecting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting backplanes on switches, routers, base-stations,
servers and video transmission systems.
The CYV15G0101DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros followed
by 1 one.
Transceiver Logic Block Diagram
x10 x11
Phase
Align
Buffer
Elasticity
Buffer
Encoder Decoder
8B/10B 8B/10B
Framer
Serializer Deserializer
TX RX
Document Number: 38-02031 Rev. *P
Page 2 of 45





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