K8S6415EBB

K8S6415ET(B)B FLASH MEMORY Document Title 64M Bit (4M x16) Muxed Burst , Multi Bank NOR Flash Memory Revision History Revision No. History 0.0 1.0 Initial Issue Draft Date October 20, 2004 Remark Revision March 22, 2005 - Specification finalized - Add the requirement and note of Quadruple word program operation Bottom boot block description is added January 09,2006 www.DataSheet4U.com 1.1 1 Revision 1.1 January, 2006 K8S6415ET(B)B FEATURES Single Voltage, 1.7V to 1.95V for Read and Write operations Organization - 4,194,304 x 16 bit ( Word Mode Only) Multiplexed Data and Address for reduction of interconnections - A/DQ0 ~ A/DQ15 Read While Program/Erase Operation Multiple Bank Architecture - 16 Banks (4Mb Partition) OTP Block : Extra 256Byte block Read Access Time (@ CL=30pF) - Asynchronous Random Access Time : www.DataSheet4U.com 90ns (54MHz) / 80ns (66MHz) - Synchronous Random Access Time : 88.5ns (54MHz) / 70ns (66MHz) - Burst Access Time : 14.5ns (54MHz) / 11ns (66MHz) Burst Length : - Continuous Linear Burst - Linear Burst : 8-word & 16-word with No-wrap & Wrap Block Architecture - Eight 4Kword blocks and one hundreds twenty seven 32Kword blocks - Bank 0 contains eight 4 Kword blocks and seven 32Kword blocks - Bank 1 ~ Bank 15 contain one hundred twenty 32Kword blocks Reduce program time using the VPP Support Single & Quad word accelerate program Power Consumption (Typical value, CL=30pF) - Burst Access Current : 30mA - Program/Erase Curr...