Clock Driver. ASM5CVF857 Datasheet

ASM5CVF857 Driver. Datasheet pdf. Equivalent

Part ASM5CVF857
Description 2.5V Wide-Range Frequency Clock Driver
Feature August 2004 rev 1.2 2.5V Wide-Range Frequency Clock Driver (60MHz – 200MHz) ASM5CVF857 condition a.
Manufacture Alliance Semiconductor
Datasheet
Download ASM5CVF857 Datasheet



ASM5CVF857
August 2004
ASM5CVF857
rev 1.2
2.5V Wide-Range Frequency Clock Driver (60MHz – 200MHz)
Features
• Low skew; low jitter PLL clock driver.
• 1 to 10 differential clock distribution (SSTL_2).
• Feedback pins for input to output synchronization.
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• PDB for power management.
• Spread spectrum tolerant inputs.
• Auto-PD when input signal removed.
• Choice of static phase offset for easy board tuning:
• -XXX = device pattern number for options listed
below:
• PCV857-025 - 0 ps
• PCV857-1300 - +50 ps
Product Description
This PLL clock buffer is designed for a VDD of 2.5V,
AVDD of 2.5V and differential data input and output
levels. ASM5CVF857 is a zero-delay buffer that
distributes a differential clock input pair (CLK_INT,
CLK_INC) to ten differential pairs of clock outputs
(CLKT[0:9], CLKC[0:9]) and one differential pair
feedback clock output (FB_OUT, FB_OUTC). The clock
outputs are controlled by the input clocks (CLK_INT,
CLKINC), the feedback clocks (FB_INT, FB_INC), the
2,5V LVCMOS input (PDB), and the analog power input
(AVDD). When input (PDB) is low while power is applied,
the receivers are disabled, the PLL is turned off, and
the differential clock outputs are tri-stated. When AVDD
is grounded, the PLL is turned off and bypassed for test
purposes.
When the input frequency is less than the operating
frequency of the PLL, approximately 20MHz, the device
will enter a low power mode. An input frequency
detection circuit on the differential inputs, independent
from the input buffers, will detect the low frequency
condition and perform the same low power features as
and when the PDB input is low. When the input
frequency increases to greater than approximately
20MHz, the PLL will be turned back on, the inputs and
outputs will be enabled, and the PLL will obtain phase
lock between the feedback clock pair (FB_INT,
FB_INC) and the input clock pair (CLK_INT, CLK_INC).
The PLL in the ASM5CVF857 clock driver uses the
input clocks (CLK_INT, CLKINC) and the feedback
clocks (FB_INT, FB_INC) to provide high-performance,
low-skew, low-jitter output differential clocks (CLKT[0:9],
CLKC[0:9]). ASM5CVF857 is also able to track spread
spectrum clock (SSC) for reduced EMI.
ASM5CVF857 is characterized for operation from 0°C
to 85°C.
Applications
• DDR Memory Modules / Zero Delay Board Fan
Out.
• Provides complete DDR DIMM logic solution with
ASM4SSTVF16857, ASM4SSTVF16859 &
ASM4SSTVF32852.
Specifications
• Meets PC3200 specification for DDR-I 400 support.
• Covers all DDRI speed grades.
Switching Characteristics
• CYCLE-CYCLE jitter : <50ps.
• OUT-OUTPUT skew: <40ps.
• Period jitter: ±30ps.
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
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ASM5CVF857
August 2004
rev 1.2
Block Diagram
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AVDD
PDB
Control
Logic
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_IN T
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ASM5CVF857
F B_O UTT
F B_O UTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CL KC 9
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 PDB
36 FB_INT
35 FB_INC
34 VDD
33 FB_OUT C
32 FB_OUT T
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
2.5V Wide-Range Frequency Clock Driver (60 MHz – 200 MHz)
Notice: The information in this document is subject to change without notice.
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