ASM5I2304A

September 2005 rev 1.4 3.3V Zero Delay Buffer Features Zero input - output propagation delay, adjustable by capacitive load on FBK input. Multiple configurations - Refer “ASM5P2304A www.DataSheet4U.com ASM5P2304A the REF pin. The PLL feedback is required to be driven to FBK pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 250pS, and the output-to-output skew is guaranteed to be less than 200pS. The ASM5P2304A has two banks of two outputs each. Multiple ASM5P2304A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 500pS. The ASM5P2304A is available in two different Configurations Table”. Input frequency range: 15MHz to 133MHz Multiple low-skew outputs. Output-output skew less than 200pS. Device-device skew less than 500pS. Two banks of four outputs. Less than 200pS Cycle-to-Cycle jitter (-1, -1H, -2, -2H). Available in space saving, 8 pin 150-mil SOIC packages. 3.3V operation. Advanced 0.35< CMOS technology. Industrial temperature available. configurations (Refer “ASM5P2304A Configurations Table). The ASM5P2304A-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The ASM5P2304A-1H is the high-drive version of the -1 and the rise and fall times on this device are much faster. The ASM5P2304A-2 allows the user to obtain REF and 1/2X or 2X frequencies...