ASM5I2305A

September 2005 rev 1.6 3.3V Zero Delay Buffer General Features ƒ ƒ ƒ 15MHz to 133MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. ƒ ƒ www.DataSheet4U.com ƒ ASM5P2309A ASM5P2305A 133MHz frequencies, and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The ASM5P2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2309A and ASM5P2305A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. All outputs have less than 200pS of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 350pS, and the output to output skew is guaranteed to be less than 250pS. The ASM5P2309A and the ASM5P2305A are available in two different configurations, as shown in the ordering information table. The ASM5P2305A-1/ ASM5P2309A-1 is the base part. The ASM5P2305A-1H/ ASM5P2309A-1H is the high drive version of the -1 and its rise and fall times are much faster than -1 part. Output-output skew less than 250pS. Device-device skew less than 700pS. One inpu...