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7032STC Dataheets PDF



Part Number 7032STC
Manufacturers Altera Corporation
Logo Altera Corporation
Description EPM7032STC
Datasheet 7032STC Datasheet7032STC Datasheet (PDF)

MAX 7000 ® Programmable Logic Device Family Data Sheet September 2005, ver. 6.7 Features... ■ ■ ■ www.DataSheet4U.com ■ ■ ■ ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S.

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MAX 7000 ® Programmable Logic Device Family Data Sheet September 2005, ver. 6.7 Features... ■ ■ ■ www.DataSheet4U.com ■ ■ ■ ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect) PCI-compliant devices available f For information on in-system programmable 3.3-V MAX 7000A or 2.5-V MAX 7000B devices, see the MAX 7000A Programmable Logic Device Family Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet. Table 1. MAX 7000 Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032 600 32 2 36 6 5 2.5 4 151.5 EPM7064 1,250 64 4 68 6 5 2.5 4 151.5 EPM7096 1,800 96 6 76 7.5 6 3 4.5 125.0 EPM7128E 2,500 128 8 100 7.5 6 3 4.5 125.0 EPM7160E 3,200 160 10 104 10 7 3 5 100.0 EPM7192E 3,750 192 12 124 12 7 3 6 90.9 EPM7256E 5,000 256 16 164 12 7 3 6 90.9 Altera Corporation DS-MAX7000-6.7 1 MAX 7000 Programmable Logic Device Family Data Sheet Table 2. MAX 7000S Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) www.DataSheet4U.com fCNT (MHz) EPM7032S 600 32 2 36 5 2.9 2.5 3.2 175.4 ■ ■ ■ ■ ■ EPM7064S 1,250 64 4 68 5 2.9 2.5 3.2 175.4 EPM7128S 2,500 128 8 100 6 3.4 2.5 4 147.1 EPM7160S 3,200 160 10 104 6 3.4 2.5 3.9 149.3 EPM7192S 3,750 192 12 124 7.5 4.1 3 4.7 125.0 EPM7256S 5,000 256 16 164 7.5 3.9 3 4.7 128.2 ...and More Features ■ ■ ■ ■ Open-drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls Programmable power-saving mode for a reduction of over 50% in each macrocell Configurable expander product-term distribution, allowing up to 32 product terms per macrocell 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages Programmable security bit for protection of proprietary designs 3.3-V or 5.0-V operation – MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages) – Pin compatible with low-voltage MAX 7000A and MAX 7000B devices Enhanced features available in MAX 7000E and MAX 7000S devices – Six pin- or logic-driven output enable signals – Two global clock signals with optional inversion – Enhanced interconnect resources for improved routability – Fast input setup times provided by a dedicated path from I/O pin to macrocell registers – Programmable output slew-rate control Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations 2 Altera Corporation MAX 7000 Programmable Logic Device Family Data Sheet ■ ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest Programming support – Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices – The BitBlasterTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX 7000S devices w w w . D a t a S h e e t 4 U c o msecond-generation MAX architecture. Fabricated with on. Altera’s General Description The MAX 7000 family of high-density, high-performance PLDs is based advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades. Table 3. MAX 7000 Speed Grades Device -5 EPM7032 EPM7032S EPM7064 EPM7064S EPM7096 EPM7128E EPM7128S EPM7160E EPM7160S EPM7192E EPM7192S EPM7256E EPM7256S Speed Grade -6 v v v v v v -7 v v v v v v v v v v v v v.


27C128 7032STC C5339


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