TSPC860

Features PowerPC® Single Issue Integer Core Precise Exception Model Extensive System Development Support – On-chip Watchpoints and Breakpoints – Program Flow Tracking – On-chip Emulation (Once) Development Interface High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power) Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O) MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with Book 1 of the PowerPC Architecture Definition) with 32 × 32-bit Fixed Point Registers – Embedded PowerPC Performs Branch Folding, Branch Prediction with www.DataSheet4U.com Conditional Prefetch, without Conditional Execution – 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU – Instruction and Data Caches are Two-way, Set Associative, Physical Address, 4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line Granularity – MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs – MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB; 16 Virtual Address Spaces and 8 Protection Groups – Advanced On-chip Emulation Debug Mode Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit) 32 Address Lines Fully Static Design VCC = +3.3V ± 5% fmax = 66 MHz Military Temperature Range: -55°C < TC < +125°C PD = 0.75 W Typical at 66 MHz Inte...