EDE5108AGBG

DATA SHEET 512M bits DDR2 SDRAM EDE5108AGBG (64M words × 8 bits) Specifications Density: 512M bits Organization ⎯ 16M words × 8 bits × 4 banks Package: 60-ball FBGA www.DataSheet4U.com ⎯ Lead-free (RoHS compliant) Power supply: VDD, VDDQ = 1.8V ± 0.1V Data rate: 667Mbps/533Mbps (max.) 1KB page size ⎯ Row address: A0 to A13 ⎯ Column address: A0 to A9 Four internal banks for concurrent operation Interface: SSTL_18 Burst lengths (BL): 4, 8 Burst type (BT): ⎯ Sequential (4, 8) ⎯ Interleave (4, 8) /CAS Latency (CL): 3, 4, 5 Precharge: auto precharge option for each burst access Driver strength: normal/weak Refresh: auto-refresh, self-refresh Features Double-data-rate architecture; two data transfers per clock cycle The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver DQS is edge-aligned with data for READs; centeraligned with data for WRITEs Differential clock inputs (CK and /CK) DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Data mask (DM) for write data Posted /CAS by programmable additive latency for better command and data bus efficiency Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality Programmable RDQS, /RDQS output for making × 8 orga...