CMOS EEPROM. 24C128 Datasheet

24C128 EEPROM. Datasheet pdf. Equivalent

24C128 Datasheet
Recommendation 24C128 Datasheet
Part 24C128
Description 2-WIRE SERIAL CMOS EEPROM
Feature 24C128; IS24C128 131,072-bit 2-WIRE SERIAL CMOS EEPROM ISSI DESCRIPTION ® PRELIMINARY INFORMATION MARCH 2.
Manufacture ISSI
Datasheet
Download 24C128 Datasheet





ISSI 24C128
IS24C128
131,072-bit 2-WIRE SERIAL
CMOS EEPROM
ISSI®
PRELIMINARY INFORMATION
MARCH 2003
FEATURES
• Organization:
– 16K-bit x 8-bit
www.DataSheet4U.com
• 64-Byte Page Write Buffer
• Two-Wire Serial Interface
– Bi-directional data transfer protocol
• Low Power CMOS Technology
– Active Current less than 2 mA (5V)
– Standby Current less than 5 µA (5V)
– Standby Current less than 2 µA (2.5V)
• Low Voltage Operation
– IS24C128-2: Vcc = 1.8V to 5.5V
– IS24C128-3: Vcc = 2.5V to 5.5V
• 400 KHz (I2C Protocol) Compatibility
• Hardware Data Protection
– Write Protect pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time Write cycle with auto clear
– 5 ms @ 2.5V
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 40 Years
• Commercial and Industrial temperature ranges
• 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP
DESCRIPTION
The IS24C128 is an electrically erasable PROM
device that uses the standard 2-wire interface for
communications. The IS24C128 contains a memory
array of 128K-bits (16,384 x 8), and is further
subdivided into 256 pages of 64 bytes each for page-
write mode. This EEPROM is offered in wide operating
voltages of 1.8V to 5.5V (IS24C128-2) and 2.5V to 5.5V
(IS24C128-3) to be compatible with most application
voltages. ISSI designed the IS24C128 to be a low-cost
and low-power 2-wire EEPROM solution. The devices
are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
TSSOP.
The IS24C128 maintains compatibility with the popular
2-wire bus protocol, so it is easy to design into
applications implementing this bus type. The simple
bus consists of the Serial Clock wire (SCL) and the
Serial Data wire (SDA). Using the bus, a Master
device such as a microcontroller is usually connected
to one or more Slave devices such as the IS24C128.
The bit stream over the SDA line includes a series of
bytes, which identifies a particular Slave device, an
instruction, an address within that Slave device, and a
series of data, if appropriate. The IS24C128 has a
Write Protect pin (WP) to allow blocking of any write
instruction transmitted over the bus.
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00B
03/11/03
1



ISSI 24C128
IS24C128
FUNCTIONAL BLOCK DIAGRAM
Vcc
SDA
www.DataSheet4SUC.cLom
WP
A0
A1
NC
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
WORD ADDRESS
COUNTER
GND
nMOS
ACK
ISSI®
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
EEPROM
ARRAY
Y
DECODER
Clock
DI/O
> DATA
REGISTER
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03



ISSI 24C128
IS24C128
PIN CONFIGURATION
8-Pin DIP and SOIC
www.DataSheet4U.com
A0 1
A1 2
NC 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
ISSI®
14-pin TSSOP
A0
A1
NC
NC
NC
NC
GND
1
2
3
4
5
6
7
14 VCC
13 WP
12 NC
11 NC
10 NC
9 SCL
8 SDA
PIN DESCRIPTIONS
A0-A1
SDA
SCL
WP
Vcc
NC
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
No Connect
Ground
SCL
This input clock pin is used to synchronize the data
transfer to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire Or'ed with other open drain
or open collector outputs. The SDA bus requires a pullup
resistor to Vcc.
A0, A1
The A0, and A1 are the device address inputs that are
hardwired or left not connected for hardware compatibility
with the 24C32/64. When pins are hardwired, as many as
four 128K devices may be addressed on a single bus
system. When the pins are not hardwired, the default A0
and A1 are zero.
WP
WP is the Write Protect pin. If the WP pin is tied to Vcc
the entire array becomes Write Protected (Read only).
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARYINFORMATION Rev.00A
03/11/03
3





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