M29F400T. 29F400T Datasheet

29F400T M29F400T. Datasheet pdf. Equivalent

29F400T Datasheet
Recommendation 29F400T Datasheet
Part 29F400T
Description M29F400T
Feature 29F400T; M29F400T M29F400B 4 Mbit (512Kb x8 or 256Kb x16, Boot Block) Single Supply Flash Memory NOT FOR NEW .
Manufacture STMicroelectronics
Datasheet
Download 29F400T Datasheet





STMicroelectronics 29F400T
M29F400T
M29F400B
4 Mbit (512Kb x8 or 256Kb x16, Boot Block)
Single Supply Flash Memory
M29F400T and M29F400B are replaced
respectively by the M29F400BT and
M29F400BB
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5V±10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 55ns
FAST PROGRAMMING TIME
– 10µs by Byte / 16µs by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code, M29F400T: 00D5h
– Device Code, M29F400B: 00D6h
DESCRIPTION
The M29F400 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or Word-
by-Word basis using only a single 5V VCC supply.
For Program and Erase operations the necessary
high voltages are generated internally. The device
can also be programmed in standard program-
mers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
NOT FOR NEW DESIGN
TSOP48 (N)
12 x 20 mm
44
1
SO44 (M)
Figure 1. Logic Diagram
VCC
18
A0-A17
15
DQ0-DQ14
W DQ15A–1
E
M29F400T
M29F400B
BYTE
G RB
RP
VSS
AI01726B
November 1999
This is information on a product stil l in production but not recommended for new designs.
1/34



STMicroelectronics 29F400T
M29F400T, M29F400B
Figure 2A. TSOP Pin Connections
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A15 1
48 A16
A14 BYTE
A13 VSS
A12 DQ15A–1
A11 DQ7
A10 DQ14
A9 DQ6
A8 DQ13
NC DQ5
NC DQ12
W DQ4
RP
NC
12 M29F400T 37
13
M29F400B
(Normal)
36
VCC
DQ11
NC DQ3
RB DQ10
NC DQ2
A17 DQ9
A7 DQ1
A6 DQ8
A5 DQ0
A4 G
A3 VSS
A2 E
A1 24
25 A0
AI01727B
Warning: NC = Not Connected.
Figure 2C. SO Pin Connections
NC
RB
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 M29F400T 34
12 M29F400B 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
AI01729B
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
Warning: NC = Not Connected.
2/34
Figure 2B. TSOP Reverse Pin Connections
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
1 48
12 M29F400T 37
13
M29F400B
(Reverse)
36
24 25
AI01728B
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
NC
A17
A7
A6
A5
A4
A3
A2
A1
Warning: NC = Not Connected.
Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7 Data Input/Outputs, Command Inputs
DQ8-DQ14 Data Input/Outputs
DQ15A–1 Data Input/Output or Address Input
E Chip Enable
G Output Enable
W Write Enable
RP Reset / Block Temporary Unprotect
RB Ready/Busy Output
B YTE
Byte/Word Organisation
VCC Supply Voltage
VSS Ground



STMicroelectronics 29F400T
M29F400T, M29F400B
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA Ambient Operating Temperature(3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
VIO (2)
Storage Temperature
Input or Output Voltages
–65 to 150
–0.6 to 7
°C
V
VCC Supply Voltage
–0.6 to 7
V
V(A9, E, G, RP) (2) A9, E, G, RP Voltage
–0.6 to 13.5
V
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Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
DESCRIPTION (Cont’d)
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cyclesof commands to a CommandInterface using
standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm) and
SO44 packages. Both normal and reverse pinouts
are available for the TSOP48 package.
Organisation
The M29F400 is organised as 512K x8 or 256K x16
bits selectable by the BYTE signal. When BYTE is
Low the Byte-wide x8 organisation is selected and
the address lines are DQ15A–1 and A0-A17. The
Data Input/Output signal DQ15A–1 acts as ad-
dress line A–1 which selects the lower or upper
Byte of the memory word for output on DQ0-DQ7,
DQ8-DQ14 remain at High impedance. When
BYTE is High the memory uses the address inputs
A0-A17 and the Data Input/Outputs DQ0-DQ15.
Memory control is provided by Chip Enable E,
Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at VID) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29F400T and M29F400B devices have an array
of 11 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and seven Main Blocks of 64 KBytes or 32
KWords. The M29F400T has the Boot Block at the
top of the memory address space and the
M29F400B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3. Each block can be erased separately, any com-
bination of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t ec t i on, Unprot ec t ion, Prot ect i on Veri f y,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
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