Bus Master. AN554 Datasheet

AN554 Master. Datasheet pdf. Equivalent

AN554 Datasheet
Recommendation AN554 Datasheet
Part AN554
Description Software Implementation of I2C Bus Master
Feature AN554; M Author: AN554 In most systems the microcontroller is the master and the external peripheral devic.
Manufacture Microchip Technology
Download AN554 Datasheet

Microchip Technology AN554
Software Implementation of I2CBus Master
Amar Palacherla
Microchip Technology Inc.
This application note describes the software
implementation of I2C interface routines for the
PIC16CXXX family of devices. Only the master mode of
I2C interface is implemented in this application note.
This implementation is for a single master communica-
tion to multiple slave I2C devices.
Some PIC16CXXX devices, such as the PIC16C64 and
PIC16C74, have on-chip hardware which implements
the I2C slave interface, while other PIC16CXXX
devices, such as the PIC16C71 and PIC16C84, do not
have the same on-chip hardware.
This application note does not describe the I2C Bus
specifications and the user is assumed to have an
understanding of the I2C Bus. For detailed information
on the bus, the user is advised to read the I2C Bus
Specification document from Philips/Signetics (order
number 98-8080-575). The I2C Bus is a two-wire serial
bus with multiple possible masters and multiple possi-
ble slaves connected to each other through two wires.
The two wires consists of a clock line (SCL) and a data
line (SDA) with both lines being bi-directional. Bi-direc-
tional communication is facilitated through the use of
wire and connection (the lines are either active-low or
passive high). The I2C Bus protocol also allows collision
detection, clock synchronization and hand-shaking for
multi-master systems. The clock is always generated by
the master, but the slave may hold it low to generate a
wait state.
In most systems the microcontroller is the master and
the external peripheral devices are slaves. In these
cases this application note can be used to attach I2C
slaves to the PIC16CXXX (the master) microcontroller.
The multi-master system is not implemented because it
is extremely difficult to meet all the I2C Bus timing spec-
ifications using software. For a true slave or multi-mas-
ter system, some interface hardware is necessary (like
START & STOP bit detection).
In addition to the low level single master I2C routines, a
collection of high level routines with various message
structures is given. These high level macros/routines
can be used as canned routines to interface to most I2C
slave devices. As an example, the test program talks to
two Serial EEPROMs (Microchip’s 24LC04
and 24LC01).
Two levels of software routines are provided. The
low-level routines “i2c_low.asm” are provided in
Appendix A and the high level routines
i2c_high.asm” are provided in Appendix B.
The messages passed (communicated on the two wire
network) are abbreviated and certain notation is used
to represent Start, Stop and other conditions. These
abbreviations are described in Table 1.
Start Condition
Stop Condition
Slave Address (for read operation)
Slave Address (for write operation)
Acknowledge condition (positive ACK)
Negative Acknowledge condition (NACK)
Data byte, D[0] represents byte 0, D[1] represents second byte
© 1997 Microchip Technology Inc.
DS00554C-page 1

Microchip Technology AN554
Message Format
In the high level routines, the basic structure of the mes-
sage is given. Every I2C slave supports one or more
message structures. For example, Microchip’s 24LC04
Serial EEPROM supports the following message (to
write a byte to Serial EEPROM at current address
counter) S-SlvAW-A-D-A-P which basically means the
following sequence of operations are required:
a) Send Start Bit
b) Send Slave Address for Write Operations
c) Expect Acknowledge
d) Send Data Byte
e) Expect Acknowledge
f) Issue a STOP Condition
Slave Address
Both 10-bit and 7-Bit addressing schemes are
implemented as specified by the I2C Bus specification.
Before calling a certain sub-routine (high level or
low-level), the address of the slave being addressed
must be loaded using either “LOAD_ADDR_8” (for 7-bit
address slaves) or “LOAD_ADDR_10” macro (for 10-bit
address slaves). These macros not only load the
address of the slaves for all the following operations,
but also setup conditions for 7- or 10-bit addressing
modes. See the macros section for more details.
In the I2C Bus, the clock (SCL line) is always provided
by the master. However, the slave can hold the line low
even though the master has released it. The master
must check this condition and wait for the slave to
release the clock line. This provides a built-in wait state
for the I2C Bus. This feature is implemented and can be
turned on or off as an assembly time option (by
configuring the _ENABLE_BUS_FREE_TIME flag to be
TRUE or FALSE). If the clock is held low for too long,
say 1 ms, then an error condition is assumed and a
T0CKI interrupt is generated.
The I2C Bus specifies both bit-by-bit and byte mode
arbitration procedures for multi-master systems.
However, the arbitration is not needed in a single
master system, and therefore is not implemented in this
application note.
Two I/O pins are used to emulate the Clock Line, SCL,
and the Data Line, SDA. In the example test program,
RB0 is used as the SCL line and RB1 as the SDA line.
On initialization, these I/O lines are configured as input
pins (tri-state) and their respective latches are loaded
with '0's. To emulate the high state (passive), these
lines are configured as inputs. To emulate the active low
state, the pins are configured as outputs (with the
assumption of having external pull-up resistors on both
For devices that have the on-chip I2C hardware (SSP
module), slope control of the I/O is implemented on the
SCK and SDA pins. For software not implemented on
the SCK and SDA pins of the SSP module, external
components for slope control of the I/O may be required
by the system.
DS00554C-page 2
© 1997 Microchip Technology Inc.

Microchip Technology AN554
Status Register (File Register “Bus_Status”)
The bit definitions of the status register are described in
the table given below. These bits reflect the status of the
I2C Bus.
Bit #
1 = Start Bit transmitted
0 = STOP condition
It is set when a fatal error condition is detected. The user must clear this bit.
This bit is set when the clock line, SCL, is stuck low.
1 = transmission in progress
1 = reception in progress
1 = transmission successfully completed
0 = error condition
1 = reception successfully completed
0 = error condition
1 = FATAL error occurred (the communication was aborted).
1 = slave sent ACK while the master was expecting an ACK.
This may happen for example if the slave was not responding to a message.
Control Register (File Register “Bus_Control”)
The bit definitions of the control register are described
in the table given below. These bits must be set by the
software prior to performing certain operations. Some
of the high level routines described later in this section
set these bits automatically.
Bit #
3, 4, 5
1 = 10-bit slave addressing
0 = 7-bit addressing.
1 = READ operation
0 = WRITE operation.
1 = last byte must be received. Used to send ACK.
Unused bits, can be used as general purpose bits.
A status bit indicating if a slave is responding. This bit is set or cleared by
calling the I2C_TEST_DEVICE macro. See description of this
A status bit indicating if a clock is stretched low for more than 1 ms, indicating
a bus error. On this time out, the operation is aborted.
© 1997 Microchip Technology Inc.
DS00554C-page 3

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