PI6CU877

PI6CU877 PLL Clock Driver for 1.8V DDR2 Memory Features PLL clock distribution optimized for DDR2 SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Differential www.DataSheet4U.com Inputs (CLK, CLK) and (FBIN, FBIN) Input OE/OS: LVCMOS Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT) External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. Operates at AVDD = 1.8V for core circuit and internal PLL, and VDDQ = 1.8V for differential output drivers Packaging (Pb-free & Green available): – 52-ball VFBGA (NF) Description PI6CU877 PLL clock driver is developed for Registered DDR2 DIMM applications with 1.8V operation and differential data input and output levels. The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to eleven differential pairs of clock outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT, FBOUT). The clock outputs are controlled by CLK/CLK, FBOUT, FBOUT, the LVCMOS (OE, OS) and the Analog Power input (AVDD). When OE is LOW the outputs except FBOUT, FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS is a program pin that must be tied to GND or VDD. When OS is high, OE will function as described above. When OS is LOW, OE has no effect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When CLK/CLK are logic ...