TSM2N7002E

TSM2N7002E 50V N-Channel Enhancement Mode MOSFET Pin assignment: 1. Gate 2. Source 3. Drain VDS = 50V RDS (on), Vgs @ 10V, Ids @ 250mA = 3Ω RDS (on), Vgs @ 5V, Ids @ 50mA = 4Ω www.DataSheet4U.com Features Advanced trench process technology High density cell design for ultra low on-resistance High input impedance High speed switching No minority carrier storage time CMOS logic compatible input No secondary breakdown Compact and low profile SOT-363 package Block Diagram Ordering Information Part No. TSM2N7002ECX TSM2N7002ECU Packing T&R (3kpcs/Reel) Package SOT-23 SOT-323 Absolute Maximum Rating (Ta = 25oC unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Maximum Power Dissipation Ta = 25 oC Ta = 75 C Operating Junction Temperature Operating Junction and Storage Temperature Range TJ TJ, TSTG o Symbol VDS VGS ID IDM PD Limit 50 ± 20 250 1.0 200 150 +150 - 55 to +150 Unit V V mA A mW o o C C Thermal Performance Parameter Lead Temperature (1/8” from case) Junction to Ambient Thermal Resistance (PCB mounted) Note: Surface mounted on FR4 board t<=5sec. Symbol TL Rθja Limit 5 625 Unit S o C/W TSM2N7002E 1-5 2004/12 rev. B Electrical Characteristics Tj = 25 oC unless otherwise noted Parameter Static Drain-Source Breakdown Voltage Drain-Source On-State Resistance Drain-Source On-State Resistance www.DataSheet4U.com Gate Threshold Voltage Zero Gate Voltage Drain Current Gate Body Leakage On-State...