Document
STY80NM60N
N-channel 600 V - 0.035 Ω - 80 A - Max247 second generation MDmesh™ Power MOSFET
Preliminary Data
Features
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Type
VDSS 600 V
RDS(on) < 0.040 Ω
ID 80 A
Pw 560 W
STY80NM60N
■ ■ ■
100% avalanche tested Low input capacitance and gate charge Low gate input resistance Max247
1 2 3
Application
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Switching applications
Description
This series of devices implements second generation MDmesh™ technology. This revolutionary Power MOSFET associates a new vertical structure to the Company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Figure 1. Internal schematic diagram
Table 1.
Device summary
Marking 80NM60N Package Max247 Packaging Tube
Order code STY80NM60N
December 2007
Rev 2
1/9
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Electrical ratings
STY80NM60N
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Electrical ratings
Table 2.
Symbol VDS VGS ID
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Gate- source voltage Drain current (continuous) at TC = 25 °C Drain current (continuous) at TC = 100 °C Drain current (pulsed) Total dissipation at TC = 25 °C Derating factor Value 600 ±25 80 50.4 320 560 4.48 15 –55 to 150 150 Unit V V A A A W W/°C V/ns °C °C
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ID IDM
(1)
PTOT dv/dt (2) Tstg Tj
Peak diode recovery voltage slope Storage temperature Max. operating junction temperature
1. Pulse width limited by safe operating area 2. ISD ≤ 80A, di/dt ≤ 400 A/µs, VDD =80% V(BR)DSS
Table 3.
Symbol Rthj-case Rthj-amb Tl
Thermal data
Parameter Thermal resistance junction-case max Thermal resistance junction-ambient max Maximum lead temperature for soldering purpose Value 0.22 30 300 Unit °C/W °C/W °C
Table 4.
Symbol IAS EAS
Avalanche characteristics
Parameter Avalanche current, repetitive or not-repetitive (pulse width limited by Tj Max) Single pulse avalanche energy (starting Tj=25°C, Id=Ias, Vdd=50 V) Value Tbd Tbd Unit A mJ
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STY80NM60N
Electrical characteristics
2
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table 5.
Symbol V(BR)DSS
On/off states
Parameter Drain-source breakdown voltage Drain source voltage slope Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 1 mA, VGS = 0 Vdd = 480 V, Id = 80 A, Vgs = 10 V VDS = Max rating VDS = Max rating, @125 °C VGS = ± 20 V VDS = VGS, ID = 250 µA VGS = 10 V, ID = 40 A 2 3 0.035 Min. 600 Tbd 1 10 100 4 0.04 Typ. Max. Unit V V/ns µA µA nA V Ω
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dv/dt (1) IDSS IGSS VGS(th) RDS(on)
1. Characteristic value at turn off on inductive load
Table 6.
Symbol gfs (1) Ciss Coss Crss Coss eq. (2) Qg Qgs Qgd Rg
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Equivalent output capacitance Total gate charge Gate-source charge Gate-drain charge Gate input resistance Test conditions VDS=15 V, ID =40 A VDS = 50 V, f = 1 MHz, VGS = 0 Min. Typ. Tbd Tbd Tbd Tbd Tbd Tbd Tbd Tbd Tbd Max. Unit S pF pF pF
VGS = 0 V, VDS = 0 V to 480 V VDD = 480 V, ID = 80 A, VGS = 10 V, (see Figure 3) f=1MHz Gate DC Bias=0 Test signal level = 20 mV open drain
pF nC nC nC Ω
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS
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Electrical characteristics
STY80NM60N
Table 7.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD = 300 V, ID = 40A RG = 4.7 Ω VGS = 10 V (see Figure 2) Min. Typ. Tbd Tbd Tbd Tbd Max. Unit ns ns ns ns
Table 8.
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Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 80 A, VGS = 0 ISD = 80 A, di/dt = 100 A/µs VDD = 100 V, Tj = 25 °C (see Figure 4) ISD = 80 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 4) Tbd Tbd Tbd Tbd Tbd Tbd Test conditions Min Typ. Max 80 320 1.5 Unit A A V ns µC A ns µC A
Symbol ISD ISDM
(1)
VSD (2) trr Qrr IRRM trr Qrr IRRM
1. Pulse width limited by safe operating area 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
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STY80NM60N
Test circuit
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Figure 2.
Test circuit
Switching times test circuit for resistive load Figure 3. Gate charge test circuit
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Figure 4.
Test circuit for inductive load Figure 5. switching and diode recovery times
Unclamped Inductive load test circuit
Figure 6.
Unclamped inductive waveform
Figure 7.
Switching time waveform
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Package mechanical data
STY80NM60N
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Package mechanical data
In order to meet .