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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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Designer's
TMOS E-FET .™ Power Field Effect Transistor TO-247 with Isolated Mounting Hole N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits www.DataSheet4U.com where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • Isolated Mounting Hole Reduces Mounting Hardware
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Data Sheet
MTW32N25E
Motorola Preferred Device
TMOS POWER FET 32 AMPERES 250 VOLTS RDS(on) = 0.08 OHM
®
D
G S
CASE 340K–01, Style 1 TO–247AE
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating Drain–Source Voltage Drain–Gate Voltage (RGS = 1.0 MΩ) Gate–Source Voltage — Continuous Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25 Ω) Thermal Resistance — Junction to Case Thermal Resistance — Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID IDM PD TJ, Tstg EAS 600 RθJC RθJA TL 0.50 40 260 °C/W °C Value 250 250 ± 20 ± 40 32 25 96 250 2.0 – 55 to 150 Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/°C °C mJ
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value. REV 2
TMOS © Motorola Motorola, Inc. 1996
Power MOSFET Transistor Device Data
1
MTW32N25E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 250 Vdc, VGS = 0 Vdc) (VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Te.