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CY9C62256 Dataheets PDF



Part Number CY9C62256
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 32K X 8 Magnetic Nonvolatile CMOS RAM
Datasheet CY9C62256 DatasheetCY9C62256 Datasheet (PDF)

PRELIMINARY CY9C62256 32K x 8 Magnetic Nonvolatile CMOS RAM Features • 100% Form, Fit, Function-compatible with 32K × 8, micropower SRAM (CY62256). — Fast Read and Write access: 70 ns — Voltage range: 4.5V–5.5V operation — Low active power: 495 mW (max.) — Low standby power, CMOS: 825 µW (max.) www.DataSheet4U.com — Data retention current: 0 µA at VCC = 0V — TTL-compatible inputs and outputs — Automatic power-down when deselected • Replaces 32K × 8 Battery Backed (BB)SRAM, EEPROM, FeRAM or Fla.

  CY9C62256   CY9C62256


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PRELIMINARY CY9C62256 32K x 8 Magnetic Nonvolatile CMOS RAM Features • 100% Form, Fit, Function-compatible with 32K × 8, micropower SRAM (CY62256). — Fast Read and Write access: 70 ns — Voltage range: 4.5V–5.5V operation — Low active power: 495 mW (max.) — Low standby power, CMOS: 825 µW (max.) www.DataSheet4U.com — Data retention current: 0 µA at VCC = 0V — TTL-compatible inputs and outputs — Automatic power-down when deselected • Replaces 32K × 8 Battery Backed (BB)SRAM, EEPROM, FeRAM or Flash memory — Data is automatically protected during power loss — Write Cycles Endurance: > 1015 Cycles — Data Retention: > 10 Years — Shielded from external magnetic fields — Extra 64 Bytes for Device Identification and tracking • Optional industrial temperature range: –40°C to +85°C • JEDEC STD 28-pin DIP (600-mil), 28-pin (300-mil) SOIC and TSOP packages — Easy memory expansion with CE and OE features Description The CY9C62256 is a high-performance CMOS nonvolatile RAM employing an advanced magnetic RAM (MRAM) process. An MRAM is nonvolatile memory that operates as a RAM. It provides data retention for more than 10 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM, EEPROM, Flash and FeRAM. Its fast writes and high write cycle endurance makes it superior to other types of nonvolatile memory. The CY9C62256 operates very similarly to other SRAM devices. Memory read and write cycles require equal times. The MRAM memory is nonvolatile due to its unique magnetic process. Unlike BBSRAM, the CY9C62256 is truly a monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the serious disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the CY9C62256 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The CY9C62256 is offered in both commercial and industrial temperature ranges. Logic Block Diagram Pin Configurations SOIC/DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 INPUTBUFFER A11 A10 A9 A8 A7 A6 A3 A2 A1 CE WE OE A5 A4 A 14 A 13 A12 A0 ROW DECODER I/O0 I/O1 SENSE AMPS Silicon Sig. 512x512 ARRA Y I/O2 I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 I/O4 I/O5 POWER COLUMN DECODER DOWN & WRITE PROTECT I/O6 I/O7 TSOP I Top View (not to scale) A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Cypress Semiconductor Corporation Document # 38-15001 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 21, 2002 PRELIMINARY Overview The CY9C62256 is a byte wide MRAM memory. The memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel asynchronous SRAM-like interface. The CY9C62256 is inherently nonvolatile and offers write protect during sudden power loss. Functional operation of the MRAM is similar to SRAM-type devices, otherwise. Memory Architecture Users access 32,768 memory locations each with 8 data bits through a parallel interface. Internally, the memory array is organized into 4 blocks of 512 rows x128 columns each. The access and cycle time are the same for read and write www.DataSheet4U.com memory operations. Unlike an EEPROM, it is not necessary to CY9C62256 Write Inhibit and Data Retention Mode This feature protects against the inadvertent write. The CY9C62256 provides full functional capability for VCC greater than 4.5V and write protects the device below 4.0V. Data is maintained in the absence of VCC. During the power-up, normal operation can resume 20 µs after VPFD is reached. Refer to page 7 for details. Sudden Power Loss—“Brown Out” The nonvolatile RAM constantly monitors VCC. Should the supply voltage decay below the operating range, the CY9C62256 automatically write-protects itself, all inputs become don’t care, and all outputs become high-impedance. Refer to page 7 for details. Silicon Signature/Device ID An extra 64 bytes of MRAM are available to the user for Device ID. By raising A9 to VCC + 2.0V and by using address locations 00(Hex) to 3F(Hex) on address pins A5, A4, A14, A13, A12 & A0 (MSB to LSB) respectively, the additional Bytes may be accessed in the same manner as the regular memory array, with 140 ns access time. Dropping A9 from input high (VCC + 2.0V) to < VCC returns the device to normal operation after 140 ns delay. Address (MSB to LSB) A5 A4 A14 A13 A12 A0 00h 01h 02h – 3Fh poll the device for a ready condition since writes occur at bus speed. Memory Operation The CY9C62256 is designed to operate in a manner similar to other bytewide memory products. For users familiar with BBSRAM, the MRAM performance is superior. For users familiar with EEPROM, Fl.


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