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P4C1023L Dataheets PDF



Part Number P4C1023L
Manufacturers Pyramid Semiconductor
Logo Pyramid Semiconductor
Description LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM
Datasheet P4C1023L DatasheetP4C1023L Datasheet (PDF)

P4C1023/P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM FEATURES VCC Current — Operating: 35mA — CMOS Standby: 100µA Access Times —55/70 ns Single 5 Volts ±10% Power Supply www.DataSheet4U.com Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 400 or 600 mil Ceramic DIP —32-Pin Ceramic SOJ DESCRIPTION The P4C1023L is a 1 Megabit low power CMOS stati.

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P4C1023/P4C1023L LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM FEATURES VCC Current — Operating: 35mA — CMOS Standby: 100µA Access Times —55/70 ns Single 5 Volts ±10% Power Supply www.DataSheet4U.com Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages —32-Pin 400 or 600 mil Ceramic DIP —32-Pin Ceramic SOJ DESCRIPTION The P4C1023L is a 1 Megabit low power CMOS static RAM organized as 128K x 8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1023L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE low) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE is HIGH or WE is LOW. The P4C1023L is packaged in a 32-pin 400 or 600 mil ceramic DIP and in a 32-pin ceramic SOJ. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DIP (C10, C11), CERAMIC SOJ (CJ1) TOP VIEW Document # SRAM126 REV OR Revised October 2005 1 P4C1023/P4C1023L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Supply Voltage 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V 4.5V ≤ VCC ≤ 5.5V MAXIMUM RATINGS Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol www.DataSheet4U.com Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current Min -0.5 -0.5 -55 -65 Max 7.0 VCC + 0.5 125 150 25 Unit V V °C °C mA mA VCC VTERM TA STG IOUT ILAT >200 DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage) Symbol VOH VOL VIH VIL ILI Parameter Output High Voltage (I/O0 - I/O7) Output Low Voltage (I/O0 - I/O7) Input High Voltage Input Low Voltage Input Leakage Current GND ≤ VIN ≤ VCC Comm. Industrial Military Comm. Industrial Military ISB VCC Current TTL Standby Current (TTL Input Levels) VCC Current CMOS Standby Current (CMOS Input Levels) VCC = 5.5V, IOUT = 0 mA CE1 = VIH or CE2 = VIL VCC = 5.5V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V 100 µA Test Conditions IOH = –1mA, VCC = 4.5V IOL = 2.1mA 2.2 -0.3 -2 -5 -10 -2 -5 -10 Min 2.4 0.4 VCC + 0.3 0.8 +2 +5 +10 +2 +5 +10 3 mA Max Unit V V V V µA GND ≤ VOUT ≤ VCC ILO Output Leakage Current CE1 ≥ VIH or CE2 ≤ VIL µA ISB1 Document # SRAM126 REV OR Page 2 of 11 P4C1023/P4C1023L CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 7 9 Unit pF pF POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Commercial www.DataSheet4U.com Note 1 -55 -70 20 25 35 20 25 35 Unit ICC Dynamic Operating Current Industrial Military mA Note 1 - Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 55 5 20 0 70 -55 Min 55 55 55 5 10 20 30 5 25 5 10 25 35 Max Min 70 70 70 -70 Max Unit ns ns ns ns ns ns ns ns ns ns ns Document # SRAM126 REV OR Page 3 of 11 P4C1023/P4C1023L READ CYCLE NO. 1 (OE CONTROLLED)(1) www.DataSheet4U.com READ CYCLE NO. 2 (ADDRESS CONTROLLED) READ CYCLE NO. 3 (CE CONTROLLED) Notes: 1. WE is HIGH for READ cycle. 2. CE and OE are LOW for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE transition LOW. 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. .


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