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CYWB0224ABM Dataheets PDF



Part Number CYWB0224ABM
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description West Bridge Astoria
Datasheet CYWB0224ABM DatasheetCYWB0224ABM Datasheet (PDF)

ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM TM TM West Bridge Astoria Features ■ ❐ ❐ ❐ ❐ ■ ■ ■ ■ ■ Pseudo CRAM interface (Antioch Interface) Pseudo NAND Flash interface SPI (slave mode) interface DMA slave support N-Xpress™ NAND Controller Technology ❐ Interleave up to 16 NANDs with 8 Chip Enables (CE#) for x8 or x16 SLC (CYWB0224ABS) or MLC (CYWB0224ABM) NAND flash devices. 4-bit Error Correction Coding Bad Block Management Static Wear Leveling Ultra low power, 1.8V core operation Low P.

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ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM TM TM West Bridge Astoria Features ■ ❐ ❐ ❐ ❐ ■ ■ ■ ■ ■ Pseudo CRAM interface (Antioch Interface) Pseudo NAND Flash interface SPI (slave mode) interface DMA slave support N-Xpress™ NAND Controller Technology ❐ Interleave up to 16 NANDs with 8 Chip Enables (CE#) for x8 or x16 SLC (CYWB0224ABS) or MLC (CYWB0224ABM) NAND flash devices. 4-bit Error Correction Coding Bad Block Management Static Wear Leveling Ultra low power, 1.8V core operation Low Power Modes Small footprint, 6x6mm VFBGA Supports I2C boot and Processor Boot Selectable Clock Input Frequencies ❐ ❐ ❐ ❐ ■ www.DataSheet4U.com Multimedia Device Support ❐ Up to 2 SD/SDIO/MMC/MMC+/CE-ATA devices ■ SLIM™ Architecture, allowing simultaneous and independent data paths between the processor and USB, and between the USB and Mass Storage. Fully backward compatible (including pin to pin) to Antioch (CYWB0124AB) High speed USB at 480 Mbps ❐ ❐ ❐ 19.2 MHz, 24 MHz, 26 MHz, and 48 MHz Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ Cellular Phones Portable Media Players Personal Digital Assistants Portable Navigation Devices Digital Cameras POS Terminals Portable Video Recorders USB 2.0 compliant Integrated USB 2.0 transceiver, smart Serial Interface Engine 16 programmable endpoints ■ Flexible Processor Interface, which supports: ❐ ❐ Multiplexing and nonMultiplexing Address and Data interface SRAM Interface Logic Block Diagram West BridgeTM AstoriaTM Control Registers Flexible Processor Interface uC Access Control P High-Speed USB 2.0 XCVR U SLIMTM SD/SDIO/ MMC+/ CEATA Block Cypress N-XpressTM Engine Configurable Storage Interface S Cypress Semiconductor Corporation Document #: 001-11710 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 7, 2007 [+] Feedback ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM Functional Overview The SLIM™ architecture The Simultaneous Link to Independent Multimedia (SLIM) architecture allows three different interfaces (P-port, S-port and U-port) to connect to each other independently. With this architecture, a device using Astoria is connected to a PC through a USB, without disturbing any of the functions of the device. The device can still access Mass Storage when the PC is synchronizing with the main processor. The SLIM architecture enables new usage models, in which a PC accesses a Mass Storage device independent of the main www.DataSheet4U.com processor, or enumerates access to both the Mass Storage and the main processor at the same time. In a handset using SLIM architecture, the user can do the following: ■ ■ ■ cation with the processor, which may have other devices connected on a shared memory bus. Asynchronous accesses can reach a bandwidth of up to 66.7 MBps. Synchronous accesses are performed at 33 MHz across 16 bits for up to 66.7 MBps bandwidth. The memory address is decoded to access any of the multiple endpoint buffers inside Astoria. These endpoints serve as buffers fo.


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