IS61NVVP51236

IS61NVVP25672 IS61NVVP51236 256K x 72 and 512K x 36, 18Mb PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle www.DataSheet4U.com Individual ISSI ADVANCE INFORMATION JULY 2002 DESCRIPTION ® Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages Single +1.8V (± 5%) power supply JTAG Boundary Scan Industrial temperature available The 16 Meg 'NVVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Cloc...