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HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History
No. www.DataShe et4U.com
0.0 0.1 0.2 0.3 Initial Draft Renewal Product Group Make a decision of PKG information Append 1.8V Operation Product to Data sheet 1) Add Errata tWC Specification 0.4 Relaxed value 50 60 tWH 15 20 tWP 25 40 tRC 50 60 tREH 15 20 tRP 30 40 tREA@ID Read 35 45 Mar.28.2004 Preliminary
History
Draft Date
Sep.17.2003 Oct.07.2003 Nov.08.2003 Dec.01.2003
Remark
Preliminary Preliminary Preliminary Preliminary
2) Modify the description of Device Operations - /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled (Enabled) (Page22) 3) Add the description of System Interface Using CE don’t care (Page37) 1) Delete Errata 2) Change Characteristics (3V Product) 0.5 tCRY Before After 60 + tr 70 + tr tREA@ID Read 35 45 Jun. 01. 2004 Preliminary
3) Delete Cache Program 0.6 1) Change TSOP1, WSOP1, FBGA package dimension 2) Edit TSOP1, WSOP1 package figures 3) Change FBGA package figure Oct. 20. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.6 / Oct. 2004 1
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
FAST BLOCK ERASE
- Block erase time: 2ms (Typ)
NAND INTERFACE
- x8 or x16 bus width. - Multiplexed Address/ Data
www.DataSheet4U.com - Pinout compatibility for all densities
STATUS REGISTER ELECTRONIC SIGNATURE
SUPPLY VOLTAGE
Sequential Row Read OPTION
: HY27USXX121M
- 3.3V device: VCC = 2.7 to 3.6V
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121M
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support - Automatic Memory Download
Memory Cell Array
- 528Mbit = 528 Bytes x 32 Pages x 4,096 Blocks
SERIAL NUMBER OPTION HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes : HY27(U/S)S08121M - x16 device: (256 + 8 spare) Words : HY27(U/S)S16121M
DATA INTEGRITY
- 100,000 Program/Erase cycles - 10 years Data Retention
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes - x16 device: (8K + 256 spare) Words
PACKAGE
- HY27US(08/16)121M-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27US(08/16)121M-T (Lead) - HY27US(08/16)121M-TP (Lead Free) - HY27US08121M-V(P) : 48-Pin WSOP1 (12 x 17 x 0.7 mm) - HY27US08121M-V (Lead) - HY27US08121M-VP (Lead Free) - HY27(U/S)S(08/16)121M-F(P) : 63-Ball FBGA (8.5 x 15 x 1.2 mm) - HY27US(08/16)121M-F (Lead) - HY27US(08/16)121M-FP (Lead Free) - HY27SS(08/16)121M-F (Lead) - HY27SS(08/16)121M-FP (Lead Free)
PAGE READ / PROGRAM
- Random access: 12us (max) - Sequential access: 50ns (min) - Page program time: 200us (typ)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.6 / Oct. 2004 2
HY27SS(08/16)121M Series HY27US(08/16)121M Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
DESCRIPTION
The HYNIX HY27(U/S)SXX121M series is a family of non-volatile Flash memories that use NAND cell technology. The devices operate 3.3V and 1.8V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x8 or x16 Input/ Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
www.DataSheet4U.com
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). A Write Protect pin is available to give a hardware protection against program and erase operations. The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/ Erase/Read (PER) Controller is currently active. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages: - 48-TSOP1 (12 x 20 x 1.2 mm) - 48-WSOP1 (12 x 17 x 0.7 mm) - 63-FBGA (8.5 x 15 x 1.2 mm, 6 x 8 ball array, 0.8mm pitch) Three options are available for the NAND Flash family: - Automatic Page 0 Read after Power-up, which allows the microcontroller to directly download .