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EPF10K50S Dataheets PDF



Part Number EPF10K50S
Manufacturers Altera Corporation
Logo Altera Corporation
Description Embedded Programmable Logic Device
Datasheet EPF10K50S DatasheetEPF10K50S Datasheet (PDF)

FLEX 10KE ® Embedded Programmable Logic Device Data Sheet January 2003, ver. 2.5 Features... ■ www.DataSheet4U.com ■ ■ Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – Dual-port capability with up to 16-bit width per embedded array block (EAB) – Logic array for general logic functions High density – 30,.

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FLEX 10KE ® Embedded Programmable Logic Device Data Sheet January 2003, ver. 2.5 Features... ■ www.DataSheet4U.com ■ ■ Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – Dual-port capability with up to 16-bit width per embedded array block (EAB) – Logic array for general logic functions High density – 30,000 to 200,000 typical gates (see Tables 1 and 2) – Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity System-level features – MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices – Low power consumption – Bidirectional I/O performance (tSU and tCO) up to 212 MHz – Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz – -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation – Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic f For information on 5.0-V FLEX® 10K or 3.3-V FLEX 10KA devices, see the FLEX 10K Embedded Programmable Logic Family Data Sheet. Table 1. FLEX 10KE Device Features Feature Typical gates (1) Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Altera Corporation DS-F10KE-2.5 EPF10K30E 30,000 119,000 1,728 6 24,576 220 EPF10K50E EPF10K50S 50,000 199,000 2,880 10 40,960 254 1 FLEX 10KE Embedded Programmable Logic Devices Data Sheet Table 2. FLEX 10KE Device Features Feature Typical gates (1) Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Note to tables: The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 31,250 gates in addition to the listed typical or maximum system gates. www.DataSheet4U.com (2) New EPF10K100B designs should use EPF10K100E devices. (1) EPF10K100E (2) 100,000 257,000 4,992 12 49,152 338 EPF10K130E 130,000 342,000 6,656 16 65,536 413 EPF10K200E EPF10K200S 200,000 513,000 9,984 24 98,304 470 ...and More Features ■ ■ Fabricated on an advanced process and operate with a 2.5-V internal supply voltage – In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port – ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication – Built-in low-skew clock distribution trees – 100% functional testing of all devices; test vectors or scan chains are not required – Pull-up on I/O pins before and during configuration Flexible interconnect – FastTrack® Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatical.


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