ICD2051 Datasheet PDF


Part Number

ICD2051

Description

Dual Programmable Clock Generator

Manufacture

Cypress Semiconductor

Total Page 8 Pages
PDF Download
Download ICD2051 Datasheet PDF


Features Datasheet pdf 1I CD20 51 fax id: 3512 ICD2051 Dual Programmable Clock Generator Features Two independent clock outputs rangin g from 320 kHz to 100 MHz • Individua lly programmable PLLs use 22-bit serial word • Low-skew ÷1,÷2, and ÷4 CLK A outputs • Phase-locked loop oscilla tor input derived from external low-fre quency reference clock (1 MHz - 25 MHz) or external crystal (2 MHz - 24 MHz) Sophisticated internal loop-filter r equires no external www.DataSheet4U.com components or manufacturing tweaks as commonly required with external filters • Three-state control disables outpu ts for test purposes (optional) • 5V operation • Low-power, high-speed CMO S technology • Available in 16-pin SOIC package Functi.
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ICD2051 Datasheet
fax id: 35121ICD2051
ICD2051
Dual Programmable Clock Generator
Features
• Two independent clock outputs ranging from 320 kHz
to 100 MHz
• Individually programmable PLLs use 22-bit serial word
• Low-skew ÷1,÷2, and ÷4 CLKA outputs
• Phase-locked loop oscillator input derived from exter-
nal low-frequency reference clock (1 MHz - 25 MHz) or
external crystal (2 MHz - 24 MHz)
• Sophisticated internal loop-filter requires no external
www.DataSheet4Uc.coommponents or manufacturing tweaks as commonly re-
quired with external filters
• Three-state control disables outputs for test purposes
(optional)
• 5V operation
• Low-power, high-speed CMOS technology
• Available in 16-pin SOIC package
Functional Description
The ICD2051 Programmable Clock Generator offers two fully
user-programmable phase-locked loops in a single package.
The outputs may be changed “on the fly” to any desired fre-
quency value between 320 kHz and 100 MHz. The ICD2051
is ideally suited for any design where one or more multiple or
varying frequencies are required, thus replacing more expen-
sive metal can oscillators.
The capability to dynamically change the output frequency
adds a whole new degree of freedom for the electrical engi-
neer. Some examples of the uses for this device include: lap-
top computers, in which slowing the speed of operation can
mean less power consumption or speeding it up can mean
faster operation; graphics board dot clocks to allow dynamic
synchronization with different brands of monitors or display
formats; and on-board test strategies where the ability to
skew a system’s desired frequency (for example ±10%) al-
lows worst case evaluations.
Logic Block Diagram
f(REF)
XTALIN
XTALOUT
÷q
Phase
Detector
Charge
Pump
VCO
7 Internal Loop Filter
µCode
Decode
÷2p
7
3 post-VCO divider select
4 VCO range select
Phase-Locked Loop Oscillator Section A
MUXREFA
MUX
GND VDD
SCLKA
DATA
22
Serial
Rcvr A
SCLKB
MUXREFB
PLL
SectionB
22
Serial
Rcvr B
÷2
÷4
MUX
CLKA
CLKA/2
CLKA/4
XBUF
CLKB
OEA
OEB
ICD2051–1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
January 1995 – Revised April 1995




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