IXFR21N100Q

HiPerFETTM Power MOSFETs ISOPLUS247TM (Electrically Isolated Back Surface) N-Channel Enhancement Mode, Low Qg, High dv/dt, Low trr, HDMOSTM Family Preliminary data sheet www.DataSheet4U.com IXFR 21N100Q VDSS ID25 RDS(on) = 1000 V = 19 A = 0.50 W trr £ 250 ns Symbol VDSS VDGR VGS VGSM ID25 ID(RMS) IDM IAR EAR EAS dv/dt PD TJ TJM Tstg TL VISOL Weight Test Conditions T J = 25°C to 150°C T J = 25°C to 150°C; RGS = 1 MW Continuous Transient TC = 25°C (MOSFET chip capability) External lead (current limit) TC = 25°C, Note 1 TC = 25°C TC = 25°C TC = 25°C IS £ IDM, di/dt £ 100 A/ms, VDD £ VDSS T J £ 150°C, RG = 2 W TC = 25°C Maximum Ratings 1000 1000 ±20 ±30 19 84 21 21 60 2.3 5 400 -55 ... +150 150 -55 ... +150 V V V V A A A A mJ J V/ns W °C °C °C °C V~ g ISOPLUS 247TM E153432 Isolated backside* G = Gate S = Source * Patent pending D = Drain 1.6 mm (0.063 in.) from case for 10 s 50/60 Hz, RMS t = 1 min 300 2500 5 Symbol Test Conditions Characteristic Values (TJ = 25°C, unless otherwise specified) min. typ. max. 1000 2.5 V 4.5 V ±100 nA TJ = 125°C 100 mA 2 mA 0.5 W Features Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation IXYS advanced low Qg process Low gate charge and capacitances - easier to drive - faster switching Low drain to tab capacitance(<30pF) Low RDS (on) HDMOSTM process Rugged polysilicon gate cell structure Rated for Unclamped Inductive Load Switching (UIS) Fast i...