HY5MS7B2BLFP

512Mbit MOBILE DDR SDRAM based on 4M x 4Bank x32 I/O Document Title 512MBit (4Bank x 4M x 32bits) MOBILE DDR SDRAM Revision History www.DataSheet4U.com Revision No. 0.1 0.2 - Initial Draft History Draft Date Sep.2006 Jan.2007 Remark Preliminary Preliminary - Added SRR function and timing diagram - Updated some AC parameters (tAC, tDQSCK, tHZ, tIS, tIH, tIPW, tDIPW, tRFC, tXSR) - Updated IDD5 - Corrected editorial errors in descriptions and figures Updated Status Register Rearranged pages to be more systematic Corrected editorial errors in descriptions and figures Corrected AC Input High/Low Level Voltage (VIH / VIL = 0.8*VDDQ / 0.2*VDDQ) - Updated IDD6 current - Updated tWTR in LPDDR333 - Reorganized and updated AC and DC Operating Conditions - Modified Status Register Read Method - Modified IDD4R and IDD4W - Added DPD option 0.3 Feb. 2007 Preliminary 0.4 Feb. 2007 Preliminary 1.0 1.1 Mar. 2007 Apr. 2007 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.1 / Apr. 2007 1 11 Mobile DDR SDRAM 512Mbit (16M x 32bit) HY5MS7B2BLF(P) Series FEATURES SUMMARY ● Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle ● Mobile DDR SDRAM INTERFACE - x32 bus width: HY5MS7B2BLFP www.DataSheet4U.com ● MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard reg...