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LM2642 Dataheets PDF



Part Number LM2642
Manufacturers National Semiconductor
Logo National Semiconductor
Description Two-Phase Synchronous Step-Down Switching Controller
Datasheet LM2642 DatasheetLM2642 Datasheet (PDF)

LM2642 Two-Phase Synchronous Step-Down Switching Controller May 2003 LM2642 Two-Phase Synchronous Step-Down Switching Controller General Description The LM2642 consists of two current mode synchronous buck regulator controllers with a switching frequency of 300kHz. The two switching regulator controllers operate 180˚ out of phase. This feature reduces the input ripple RMS current, thereby significantly reducing the required input capacitance. The two switching regulator outputs can also be par.

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LM2642 Two-Phase Synchronous Step-Down Switching Controller May 2003 LM2642 Two-Phase Synchronous Step-Down Switching Controller General Description The LM2642 consists of two current mode synchronous buck regulator controllers with a switching frequency of 300kHz. The two switching regulator controllers operate 180˚ out of phase. This feature reduces the input ripple RMS current, thereby significantly reducing the required input capacitance. The two switching regulator outputs can also be paralleled to operate as a dual-phase single output regulator. The output of each channel can be independently adjusted from 1.3 to VIN • maximum duty cycle. An internal 5V rail is also available externally for driving bootstrap circuitry. Current-mode feedback control assures excellent line and load regulation and a wide loop bandwidth for excellent response to fast load transients. Current is sensed across either the Vds of the top FET or across an external currentsense resistor connected in series with the drain of the top FET. Current limit is independently adjustable for each channel. The LM2642 features analog soft-start circuitry that is independent of the output load and output capacitance. This makes the soft-start behavior more predictable and controllable than traditional soft-start circuits. A PGOOD1 pin is provided to monitor the dc output of channel 1. Over-voltage protection is available for both outputs. A UV-Delay pin is also available to allow delayed shut off time for the IC during an output under-voltage event. Features n n n n n n n n n n n n n n n n Two synchronous buck regulators 180˚ out of phase operation 4.5V to 30V input range Power good function monitors Ch.1 37µA Shutdown current 0.04% (typical) line and load regulation error Current mode control with or without a sense resistor Independent enable/soft-start pins allow simple sequential startup configuration. Configurable for single output parallel operation. (See Figure 2). Adjustable cycle-by-cycle current limit Input under-voltage lockout Output over-voltage latch protection Output under-voltage protection with delay Thermal shutdown Self discharge of output capacitors when the regulator is OFF TSSOP package Applications n n n n Embedded computer systems High end gaming systems Set-top boxes WebPAD Block Diagram 20046201 © 2003 National Semiconductor Corporation DS200462 www.national.com LM2642 Connection Diagram TOP VIEW 20046202 28-Lead TSSOP (MTC) Order Number LM2642MTC See NS Package Number MTC28 Pin Descriptions KS1 (Pin 1): The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to connect this pin to the current sense point. It should be connected to VIN as close as possible to the node of the current sense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the upper MOSFET. ILIM1 (Pin 2): Current limit threshold setting for Channel 1. It sinks a constant current of 10 µA, which is converted to a voltage across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the VDS of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current condition has occurred in Channel 1. COMP1 (Pin 3): Compensation pin for Channel 1. This is the output of the internal transconductance amplifier. The compensation network should be connected between this pin and the signal ground, SGND (Pin 8). FB1 (Pin 4): Feedback input for channel 1. Connect to VOUT through a voltage divider to set the channel 1 output voltage. PGOOD1 (Pin 5): An open-drain power-good output for Channel 1. It is ’LOW’ (low impedance to ground) whenever the output voltage of Channel 1 falls outside of a +15% to -9% window. PGOOD1 stays latched in a ’LOW’ state during OVP or UVP on either channel. It will recover to a ’HIGH’ state (high impedance to ground) after a Channel 1 output under-voltage event ( < 91%) when the output returns to within 6% of its nominal value. See Operation Descriptions for details. UV_DELAY (Pin 6): A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5µA current source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to ground will disable the output under-voltage protection. VLIN5 (Pin 7): The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and supplies the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7µF capacitor. SGND (Pin 8): The ground connection for the signal-level circuitry. It should be connected to the ground rail of the system. ON/SS1 (Pin 9): Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V (open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole c.


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