Clock Driver. CY29350 Datasheet

CY29350 Driver. Datasheet pdf. Equivalent

Part CY29350
Description 9-Output Clock Driver
Feature CY29350 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver Features • Output frequency range: 25 MHz to 2.
Manufacture Cypress Semiconductor
Datasheet
Download CY29350 Datasheet




CY29350
CY29350
2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
Features
• Output frequency range: 25 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 31.25 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2.5% max Output duty cycle variation
www.DataSheet4UN.cinome Clock outputs: Drive up to 18 clock lines
• Two reference clock inputs: Xtal or LVCMOS
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9350
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0mm TQFP package
Block Diagram
Functional Description
The CY29350 is a low-voltage high-performance 200-MHz
PLL-based clock driver designed for high speed clock distri-
bution applications.
The CY29350 features Xtal and LVCMOS reference clock
inputs and provides nine outputs partitioned in four banks of 1,
1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4
while the other banks divide by 4 or 8 per SEL(A:D) settings,
see . These dividers allow output to input ratios of 16:1, 8:1,
4:1, and 2:1. Each LVCMOS compatible output can drive 50
series or parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. The internal
VCO is running at multiples of the input reference clock set by
the feedback divider, see Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
SELA
PLL_EN
REF_SEL
TCLK
XIN
XOUT
OSC
FB_SEL
SELB
SELC
Phase
Detector
VCO
200 -
500MHz
LPF
÷16 / ÷32
SELD
÷2 / ÷4
÷4 / ÷8
÷4 / ÷8
÷4 / ÷8
OE#
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
AVDD
FB_SEL
SELA
SELB
SELC
SELD
AVSS
XOUT
1 24 QC0
2 23 VDDQC
3 22 QC1
4
5
CY29350
21
20
VSS
QD0
6 19 VDDQD
7 18 QD1
8 17 VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07474 Rev. *A
Revised July 26, 2004



CY29350
CY29350
Pin Definitions[1]
Pin
8
9
30
28
26
22, 24
12, 14, 16, 18, 20
2
www.DataSheet41U0.com
31
32
3, 4, 5, 6
27
23
15, 19
1
11
Name
XOUT
XIN
TCLK
QA
QB
QC(1:0)
QD(4:0)
FB_SEL
OE#
PLL_EN
REF_SEL
SEL(A:D)
VDDQB
VDDQC
VDDQD
AVDD
VDD
7 AVSS
13, 17, 21, 25, 29 VSS
I/O
O
I
I, PD
O
O
O
O
I, PD
I, PD
I, PU
I, PD
I, PD
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Type
Analog
Analog
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDD
VDD
VDD
VDD
VDD
Ground
Ground
Description
Oscillator Output. Connect to a crystal.
Oscillator Input. Connect to a crystal.
LVCMOS/LVTTL reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Clock output bank D
Internal Feedback Select Input. See Table 1.
Output enable/disable input. See Table 2.
PLL enable/disable input. See Table 2.
Reference select input. See Table 2.
Frequency select input, Bank (A:D). See Table 2.
2.5V or 3.3V Power supply for bank B output clock[2,3]
2.5V or 3.3V Power supply for bank C output clocks[2,3]
2.5V or 3.3V Power supply for bank D output clocks[2,3]
2.5V or 3.3V Power supply for PLL[2,3]
2.5V or 3.3V Power supply for core, inputs, and bank A output
clock[2,3]
Analog ground
Common ground
Table 1. Frequency Table
FB_SEL
0
1
Feedback Divider
÷32
÷16
VCO
Input Clock * 32
Input Clock * 16
Input Frequency Range
(AVDD = 3.3V)
6.25 MHz to 15.625 MHz
12.5 MHz to 31.25 MHz
Input Frequency Range
(AVDD = 2.5V)
6.25 MHz to 11.875 MHz
12.5 MHz to 23.75 MHz
Table 2. Function Table
Control
Default
0
1
REF_SEL
0
Xtal
TCLK
PLL_EN
1 Bypass mode, PLL disabled. The input PLL enabled. The VCO output connects to the
clock connects to the output dividers
output dividers
OE#
0
Outputs enabled
Outputs disabled (three-state)
FB_SEL
0
Feedback divider ÷ 32
Feedback divider ÷ 16
SELA
0 ÷ 2 (Bank A)
÷ 4 (Bank A )
SELB
0 ÷ 4 (Bank B)
÷ 8 (Bank B)
SELC
0 ÷ 4 (Bank C)
÷ 8 (Bank C)
SELD
0 ÷ 4 (Bank D)
÷ 8 (Bank D)
Notes:
1. PU = Internal pull-up, PD = Internal pull-down.
2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply
pins.
Document #: 38-07474 Rev. *A
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