Delay Buffer. CY29352 Datasheet
2.5V or 3.3V, 200 MHz,
11 Output Zero Delay Buffer
■ Output frequency range: 16.67 MHz to 200 MHz
■ Input frequency range: 16.67 MHz to 200 MHz
■ 2.5V or 3.3V operation
■ Split 2.5V and 3.3V outputs
www.DataShee■t4±U2.c%ommaximum output duty cycle variation
■ 11 clock outputs: drive up to 22 clock lines
■ LVCMOS reference clock input
■ 125 ps maximum output-output skew
■ PLL bypass mode
■ Spread Aware™
■ Output enable and disable
■ Pin compatible with MPC9352 and MPC952
■ Industrial temperature range: –40°C to +85°C
■ 32-pin 1.4 mm TQFP package
The CY29352 is a low voltage high performance 200 MHz PLL
based zero delay buffer designed for high speed clock distri-
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in three banks of five, four, and
two outputs. Bank A divides the VCO output by four and six
while bank B divides by four and two, and bank C divides by
two and four per SEL(A:C) settings, see Table 3 on page 3.
These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1,
2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output drives one or two
traces, giving the device an effective fanout of 1:22.
The PLL is stable if the VCO is configured to run between 200
MHz to 500 MHz. This allows a wide range of output
frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO runs at multiples of the
input reference clock set by the feedback divider, see Table 2
on page 3. When PLL_EN# is HIGH, PLL is bypassed and the
reference clock directly feeds the output dividers. This mode
is fully static and the minimum input clock frequency specifi-
cation does not apply.
÷2 / QC0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07476 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 14, 2008
Figure 1. Pin Diagram - 32-pin 1.4 mm TQFP package
1 24 VSS
2 23 QB1
3 22 QB0
CY293524 21 VDDQB
5 20 VDDQA
6 19 QA4
7 18 QA3
8 17 VSS
Table 1. Pin Definition - 32-pin 1.4 mm TQFP package
12, 14, 15, 18, 19 QA(0:4)
22, 23, 26, 27 QB(0:3)
2, 3, 4
13, 17, 24, 28, 29 VSS
Reference clock input
Clock output bank A
Clock output bank B
Clock output bank C
Feedback clock input. Connect to an output for normal operation.
This input must be at the same voltage rail as input reference clock,
see Table 2 on page 3.
VCO divider select input, see Table 3 on page 3.
Master reset or output enable and disable input, see Table 3 on page
PLL enable and disable input, see Table 3 on page 3.
Frequency select input, bank (A:C), see Table 3 on page 3.
2.5V or 3.3V power supply for bank A output clocks [2,3]
2.5V or 3.3V power supply for bank B output clocks [2,3]
2.5V or 3.3V power supply for bank C output clocks [2,3]
2.5V or 3.3V power supply for PLL [2,3]
2.5V or 3.3V power supply for core and inputs [2,3]
1. PD = Internal pull down.
2. A 0.1-μF bypass capacitor must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, the
high frequency filtering characteristics are cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
Document Number: 38-07476 Rev. *B
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