N2DS12H16CT

N2DS12H16CT 128Mb DDR SDRAM Features CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR400 DDR333 DDR266B (-5/-5T) (-6K)* (-75B) 2.5 166 133 100 3 200 166 133 * -6K also meets DDR266A Spec (MHz-CL-t RCD-tRP = 133-2.5-3-3) CAS Latency Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is centeraligned with data for writes Differential clock inputs (CK and CK) www.DataSheet4U.com Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2 / 2.5(DDR333), 2.5 / 3(DDR400) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) I/O VDDQ = VDD = 2.6V ± 0.1V(DDR400) VDDQ = VDD = 2.5V ± 0.2V (DDR333) -5/-5T Speed sort; Support PC3200/2700/2100 modules -6K Speed sort: Supports PC2700/PC2100 modules -75B Speed sort: Supports PC2100 modules Description The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double-data-rate architecture to achiev...