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KM681001A Dataheets PDF



Part Number KM681001A
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 128K x 8 Bit High-Speed CMOS Static RAM
Datasheet KM681001A DatasheetKM681001A Datasheet (PDF)

PRELIMINARY KM681001A Document Title 128Kx8 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Release to final Data Sheet. 2.1. Delete Preliminary Update D.C and A.C parameters. 3.1. Update D.C parameters Previous spec. Items (15/17/20ns part) Icc 190/180/170mA Isb 30mA I.

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PRELIMINARY KM681001A Document Title 128Kx8 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Release to final Data Sheet. 2.1. Delete Preliminary Update D.C and A.C parameters. 3.1. Update D.C parameters Previous spec. Items (15/17/20ns part) Icc 190/180/170mA Isb 30mA Isb1 10mA 3.2. Update A.C parameters Previous spec. Items (15/17/20ns part) tCW 12/12/13ns tAW 12/12/13ns tWP1(OE=H) 12/12/13ns tDW 8/9/10ns Draft Data Jan. 18th, 1995 Apr. 22th, 1995 Remark Design Target Preliminary www.DataSheet4U.com Rev. 2.0 Feb. 29th, 1996 Final Rev. 3.0 Jul. 16th, 1996 Updated spec. (15/17/20ns part) 165/165/160mA 25mA 8mA Updated spec. (15/17/20ns part) 10/11/12ns 10/11/12ns 10/11/12ns 7/8/9ns Jun. 2nd, 1997 Final Rev. 4.0 Update D.C and A.C parameters and add 300mil-SOJ PKG. 4. 1. Add 32-Pin 300mil-SOJ Package. 4. 2. Update D.C and A.C parameters. Previous spec. Updated spec. Items (15/17/20ns part) (15/17/20ns part) Icc 165/165/160mA 125/125/120mA tOW 3/4/5ns 3/3/3ns 4.3. Add the test condition for Voh1 with Vcc=5V±5% at 25°C 4.4. Add timing diagram to define tWP1 as ″(Timing Wave Form of Write Cycle(OE=Low Fixed)″ 5.1. Delete 17ns Part 5.2. Delete 32-SOJ-300 Package Final Rev. 5.0 Feb. 25th, 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 5.0 February 1998 PRELIMINARY KM681001A 128K x 8 Bit High-Speed CMOS Static RAM FEATURES • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating KM681001A - 15 : 125mA(Max.) KM681001A - 20 : 120mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation -No Clock or Refresh required • Three State Outputs www.DataSheet4U.com • Standard Pin Configuration KM681001AJ : 32-SOJ-400 CMOS SRAM GENERAL DESCRIPTION The KM681001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681001A uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using Samsung′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681001A is packaged in a 400mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) N.C A0 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 Vcc A16 30 CS2 29 28 27 26 WE A15 A14 A13 A12 OE A11 FUNCTIONAL BLOCK DIAGRAM Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A12 A2 A3 A4 Pre-Charge Circuit A5 A6 A7 SOJ 25 24 23 Row Select A8 Memory Array 512 Rows 256x8 Columns A9 A10 I/O1 I/O2 I/O3 22 CS1 21 I/O8 20 I/O7 19 I/O6 18 I/O5 17 I/O4 I/O1 ~I/O8 Data Cont. CLK Gen. I/O Circuit Column Select Vss A8 A9 A10 A11 A13 A14 A15 A16 PIN FUNCTION Pin Name Pin Function Address Inputs Write Enable Chip Selects Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection A0 - A16 WE CS1, CS2 OE I/O1 ~ I/O8 VCC VSS N.C CS2 CS1 WE OE -2- Rev 5.0 February 1998 PRELIMINARY KM681001A ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN, VOUT VCC PD TSTG TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 Unit V V CMOS SRAM W °C °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. www.DataSheet4U.com RECOMMENDED DC OPERATING CONDITIONS(TA = 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5* Typ 5.0 0 Max 5.5 0 VCC + 0.5** 0.8 Unit V V V V * VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA ** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS1=VIL, CS2=VIH, VIN=VIH or VIL, IOUT=0mA Min. Cy.


TC74HC597AP KM681001A BZT52C28WS


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