CY7C9536B

CONFIDENTIAL CY7C9536B OC-48/STM-16 Framer with VC - POSIC2GVC™ Features OC-48/STS-48/STM-16, OC-12/STS-12/STM-4, OC-3/STS3/STM-1 rates, concatenated and non-concatenated Complies with ITU-Standards G.707/Y.1322 and G.783[1,2] www.DataSheet4U.com PPP control packets optionally sent to host CPU interface MAC/layer 3 address look up and tagging. Programmable A1A2 processing bypass in Rx direction with frame sync input Complete section overhead (SOH), line overhead (LOH), and path overhead (POH) processing APS extraction, CPU interrupt generation, and programmable insertion of APS byte Line side APS port interface Provision for protection switching on SONET/SDH port Programmable PRBS generator and receiver Serial port to access line/section data communication channel (DCC) and voice communication channel (VCC) Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3 interface[14,15] 16-bit/32-bit host CPU interface bus JTAG and boundary scan Glueless interface with Cypress CYS25G0101DX OC-48 PHY 0.18-um CMOS, 504-pin BGA package +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for HSTL/LVPECL I/O supply, and +0.75V/2.0V reference Complies with Bellcore GR253 rev.1, 1997 [3] Channelized operation: supports 16xOC-3 and 4xOC-12 within OC-48 stream Supports TUG3 mapping in SDH mode Virtual concatenation enables secure and dedicated bandwidth provisioning[4] Up to 16 channels From 50-Mbps to 1.2-Gbps bandwidth per channel STS-1 and STS-3c gra...