17S30A

0 R Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A) 5 DS078 (v1.8) November 18, 2002 0 Advance Product Specification Features Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices Simple interface to the Spartan device Programmable reset polarity (active High or active Low) Low-power CMOS floating gate process www.DataSheet4U.com 3.3V PROM Available in compact plastic 8-pin DIP, 8-pin VOIC, 20-pin SOIC, or 44-pin VQFP packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Guaranteed 20-year life data retention Introduction The XC17S00A family of PROMs provide an easy-to-use, cost-effective method for storing Spartan-II/Spartan-IIE device configuration bitstreams. When the Spartan device is in Master Serial mode, it generates a configuration clock that drives the Spartan PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the Spartan device D IN pin. The Spartan device generates the appropriate number of clock pulses to complete the Spartan-II/IIE FPGA XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200 XC2S50E XC2S100E XC2S150E(1) XC2S200E XC2S300E XC2S400E XC2S600E configuration. Once configured, it disables the PROM. When a Spartan device is in Slave Serial mode, the PROM and the Spartan device mu...