TSC695F

Features Integer Unit Based on SPARC V7 High-performance RISC Architecture Optimized Integrated 32/64-bit Floating-point Unit On-chip Peripherals – EDAC and Parity Generator and Checker – Memory Interface Chip Select Generator Waitstate Generation Memory Protection – DMA Arbiter – Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) www.DataSheet4U.com – Interrupt Controller with 5 External Inputs – General Purpose Interface (GPI) – Dual UART Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes Fully Static Design Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs Operating Range: 4.5V to 5.5V(1) -55°C to +125°C Total Dose Radiation Capability (Parametric and Functional): 300 KRADs (Si) SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case) Latch-up Immunity Better than (LET) 100 MeV-cm2/mg Quality Grades: ESA SCC, QML Q or V Package: 256 MQFPF; Bare Die Note: 1. For 3.3V capability see the TSC695FL datasheet on the Atmel site. Rad-Hard 32-bit SPARC Embedded Processor TSC695F Description The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full develo...