SMPTE-259M/DVB-ASI Scrambler/Controller. CY7C9235A Datasheet
• Fully compatible with SMPTE-259M
• Fully compatible with DVB-ASI
• Operates from a single +5V supply
• 44-pin PLCC package
• Encodes both 8- and 10-bit parallel digital streams for
27M characters/sec (270 Mbits/sec serial)
• Operates with CY7B9234 SMPTE HOTLink
• ×9 + ×4 + 1 scrambler and NRZI encoder may be
bypassed for raw data output
The CY7C9235A is a CMOS integrated circuit designed to
encode SMPTE-125M bit-parallel digital characters (or other
data formats) using the SMPTE-259M encoding rules.
Following encoding, the characters are output as bit-parallel
characters ready for serialization. The encoded outputs of the
CY7C9235A are designed to be directly mated to a CY7B9234
HOTLink transmitter, which then converts the bit-parallel
characters into a SMPTE-259M compatible high-speed serial
This device performs both TRS (sync) detection and filtering,
data scrambling with the SMPTE-259M ×9 + ×4 + 1 algorithm,
and NRZ-to-NRZI encoding. These functions operate at a 27
MHz character rate. For those systems operating with
non-SMPTE-259M compliant video streams (or for diagnostic
purposes), the scrambler and NRZI encoding functions can be
The CY7C9235A also contains the necessary multiplexers,
control inputs, and outputs, to sequence out a DVB-ASI
compliant video stream. DVB-ASI operation is enabled
through activation of a single input signal. This allows a single
serial output port to support both SMPTE and DVB data
streams under software or hardware control.
In DVB-ASI mode the CY7C9235A operates with two enable
signals (ENA and ENN) to allow data to be presented from
either synchronous (clocked) or asynchronous FIFOs. When
data is not available, the CY7C9235A ensures that the proper
fill character (K28.5) is generated by the attached CY7B9234
The CY7C9235A operates from a single +5V supply. It is
available in a 44-pin PLCC space saving package.
Logic Block Diagram
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Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02082 Rev. **
Revised October 13, 2003
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Pin Descriptions CY7C9235A SMPTE-259M Encoder
Enable Parallel Data. If ENA is LOW at the rising edge of CKW, the data present on the PD0−9 inputs
is latched, and routed to the Q0–9 outputs. This pin is only interpreted when DVB_EN is active (LOW).
If the CY7C9235A is only used in SMPTE-259M mode this signal should be tied to VSS.
Enable Next Parallel Data. If ENN is LOW at the rising edge of CKW, the data present on the PD0–9
inputs at the next rising edge of TXCLK is latched, and routed to the Q0–9 outputs. This pin is only
interpreted when DVB_EN is active (LOW). If the CY7C9235A is only used in SMPTE-259M mode
this signal should be tied to VSS.
Bypass SMPTE Encoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at
the rising edge of CKW (and DVB_EN is HIGH), the data latched into the input register is routed
around both the SMPTE scrambler and the NRZI encoder and presented to the output register. If
BYPASS is LOW at the rising edge of the CKW clock (and DVB_EN is HIGH), the data present in
the input register is routed through the SMPTE scrambler and NRZI encoder.
TRS Character Detected. This output indicates when a character used in the TRS sequence is
detected in the input register. If the data contains any of the reserved characters of 000–003 or
3FC–3FF in 10-bit hex, the output will be LOW for one clock period. If the character in the input
register is any other pattern (or DVB_EN is LOW) this output will remain HIGH.
TRS Character Filter. This signal controls an internal filter that converts the low-order two bits of all
TRS characters to same state as the upper eight bits. This allows a proper 30-bit TRS ID to be
generated when the CY7C9235A is operated with 8-bit or non-standard video streams. When this
signal is LOW, all characters from 000–003 are converted to 000, and all characters from 3FC–3FF
are converted to 3FF. When TRS_FILT is disabled (HIGH), all characters are passed to the scrambler
without modification. This signal has no effect when DVB_EN is active (LOW).
Send Violation Symbol Enable. This input is only valid when DVB_EN is active (LOW). If SVS_EN
is HIGH and a HIGH input is present on PD9, Q9 will also be high on a following clock cycle, forcing
the CY7B9234 serializer to generate an invalid 8B/10B character. If SVS_EN is LOW, the level
present on PD9 is ignored and Q9 is forced to a LOW state.
Document #: 38-02082 Rev. **
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